STLC5046 Registers addresses
Doc ID 7052 Rev 5 31/51
3.1.19 Receive Time Slot channel #0 (DRA0)
Addr=17h; Reset Value=00h
EN0=0: Disable reception of selected time slot.
EN0=1: Selected receive time slot on DR input is PCM decoded and transferred to VFRO0
output.
R06..0:Define receive time slot number (0 to 127) on carrying the PCM signal to be decoded
and transferred to VFRO0 output.If linear mode is selected (LIN=1 of CONF register) the 16
bits will be used as linear code as follows: the 8most significative bits in the programmed
time slot, the 8 least significative bits in the following timeslot.
Example: if R06..R00=00:
Pin-strap value (value 80h):
Referred to FS0.
3.1.20 Receive Time Slot channel #1 (DRA1)
Addr=18h; Reset Value=00h
EN1=0: Disable reception of selected time slot.
EN1=1: Selected receive time slot on DR input is PCM decoded and transferred to VFRO1
output.
R16..0:Define receive time slot number (0 to 127) on carrying the PCM signal to be decoded
and transferred to VFRO1 output.If linear mode is selected (LIN=1 of CONF register) the 16
bits will be used as linear code as follows: the 8most significative bits in the programmed
time slot, the 8 least significative bits in the following timeslot.
Example: if R16..R10=00:
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
EN0 R06 R05 R04 R03 R02 R01 R00
TS0 TS1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
10000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
EN0 R16 R15 R14 R13 R12 R11 R10
Registers addresses STLC5046
32/51 Doc ID 7052 Rev 5
Pin-strap value (value 80h):
Referred to FS1.
3.1.21 Receive Time Slot channel #2 (DRA2)
Addr=19h; Reset Value=00h
EN2=0: Disable reception of selected time slot.
EN2=1: Selected receive time slot on DR input is PCM decoded and transferred to VFRO1
output.
R26..0:Define receive time slot number (0 to 127) on carrying the PCM signal to be decoded
and transferred to VFRO2 output.If linear mode is selected (LIN=1 of CONF register) the 16
bits will be used as linear code as follows: the 8most significative bits in the programmed
time slot, the 8 least significative bits in the following timeslot.
Example: if R26..R20=00:
Pin-strap value (value 80h):
Referred to FS2.
3.1.22 Receive Time Slot channel #3 (DRA3)
Addr=1Ah; Reset Value=00h
TS0 TS1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
10000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
EN0 R26 R25 R24 R23 R22 R21 R20
TS0 TS1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
10000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
EN0 R36 R35 R34 R33 R32 R31 R30
STLC5046 Registers addresses
Doc ID 7052 Rev 5 33/51
EN3=0: Disable reception of selected time slot.
EN3=1: Selected receive time slot on DR input is PCM decoded and transferred to VFRO1
output.
R36..0:Define receive time slot number (0 to 127) on carrying the PCM signal to be decoded
and transferred to VFRO2 output.If linear mode is selected (LIN=1 of CONF register) the 16
bits will be used as linear code as follows: the 8most significative bits in the programmed
time slot, the 8 least significative bits in the following timeslot.
Example: if R36..R30=00:
Pin-strap value (value 80h):
Referred to FS3.
3.1.23 PCM Shift register (PCMSH)
Addr=1Bh; Reset Value=00h
XS2..0:Effective start of the TX frame is the programmed values of clock pulses (0 to 7) after
the FS rising edge.
RS2..0:Effective start of the RX frame is the programmed values of clock pulses (0 to 7)
after the FS rising edge.
Pin-strap value (value=00h):
3.1.24 Interrupt Mask register for I/O port (DMASK)
Addr=1Ch; Reset Value=FFh
Addr=1Dh; Reset Value=XFh
TS0 TS1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
10000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
XS2 XS1 XS0 RS2 RS1 RS0
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

STLC5046

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
Interface - CODECs Prog 4-Ch CODEC/Filt
Lifecycle:
New from this manufacturer.
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