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STLC5046

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51
STLC5046 Block diagram and pin connection
Doc ID 7052 Rev 5 7/51
1.1 Pin description
Table 2. I/O definition
Type Definition
AI Analog input
AO Analog output
ODO Open drain output
DI Digital input
DO Digital output
DIO Digital input/output
DTO Digital tristate output
DPS Digital power supply
APS Analog power supply
Table 3. Pin description
N. Name Type Function
Analog
33 VFRO0 AO
Receive analog amplifier output channel 0. PCM data received on the programmed
time slot on DR input is decoded and appears at this output.
39 VFRO1 AO
Receive analog amplifier output channel 1. PCM data received on the programmed
time slot on DR input is decoded and appears at this output.
42 VFRO2 AO
Receive analog amplifier output channel 2. PCM data received on the programmed
time slot on DR input is decoded and appears at this output.
48 VFRO3 AO
Receive analog amplifier output channel 3. PCM data received on the programmed
time slot on DR input is decoded and appears at this output.
35 VFXI0 AI TX Input amplifier channel 0. Typ 1M.input impedance
38 VFXI1 AI TX Input amplifier channel 1. Typ 1M.input impedance
43 VFXI2 AI TX Input amplifier channel 2. Typ 1M.input impedance
46 VFXI3 AI TX Input amplifier channel 3. Typ 1M.input impedance
40 CAP AI
AGND voltage filter pin. A 100nF capacitor must be connected between ground and
this pin.
Power supply
25, 36,
37, 44,
45, 56,
VCC/0/1/2
/3/ 4/5
APS
Total 6 pins: 3.3 V analog power supplies, should be shorted together, require
100nF decoupling capacitor to VEE.
26,30,
31, 50,
51,55
VEE/0/1/2
/3/ 4/5
APS Total 6 pins: analog ground, should be shorted together.
9 VDD DPS Digital power supply 3.3 V, require 100 nF decoupling capacitor to VSS.
8 VSS DPS Digital ground
Block diagram and pin connection STLC5046
8/51 Doc ID 7052 Rev 5
41 SUB DPS
Substrate connection. Must be shorted together with VEE and VSS pins as close as
possible the chip.
Not connected
15, 16,
17, 18,
32, 34,
47, 49,
64
N.C. Not connected.
1,2,63 RES Reserved: must be left not connected.
Digital
27 M0 DI Mode select, see M1
54 M1 DI
13 MCLK DI
Master clock input. Four possible frequencies can be used: 1.536/1.544 MHz;
2.048 MHz; 4.096 MHz; 8.192 MHz. The device automatically detect the frequency
applied. This signal is also used as bit clock and it is used to shift data into and out
of the DR and DX pins.
12 TSX
ODO
Transmit time slot (open drain output, 3.2mA). Normally it is floating in high
impedance state except when a time slot is active on the DX output. In this case
TSX
output pulls low to enable the backplane line driver.
11 DX DTO
Transmit PCM interface. It remains in high impedance state except during the
assigned time slots during which the PCM data byte is shifted out on the rising edge
of MCLK.
10 DR DI
Receive PCM interface. It remains inactive except during the assigned receive time
slots during which the PCM data byte is shifted in on the falling edge of MCLK.
61 IO7 DIO
SLIC control I/O pin #7. Can be programmed as input or output via DIR register.
Depending on content of CONF register can be a static input/output or a dynamic
input/output synchronized with the CSn
output signals controlling the SLICs.
60 IO8 DIO SLIC control I/O pin #8. (see IO7 description).
59 IO9 DIO SLIC control I/O pin #9. (see IO7 description).
58 IO10 DIO SLIC control I/O pin #10. (see IO7 description).
57 IO11 DIO SLIC control I/O pin #11. (see IO7 description).
Digital (dual mode)
Table 3. Pin description (continued)
N. Name Type Function
M1 M0 Mode select
0
1
0
1
1
0
0
1
Pin-strap mode: basic functions selected by proper pin strapping
MCU mode: device controlled via serial interface
Reset status
Not allowed
STLC5046 Block diagram and pin connection
Doc ID 7052 Rev 5 9/51
14 FS/FS0 DI
MCU control mode: FS.
Frame Sync. Pulse. A pulse or a square wave waveform with an 8kHz repetition
rate is applied to this pin to define the start of the receive and transmit frame.
Effective start of the frame can be then shifted of up to 7 clock pulses independently
in receive and transmit directions by proper programming of the PCMSH register.
Pin-strap control mode: FS0.
Frame Sync. pulse of channel #0. One MCLK cycle long, starts PCM data transfer
in the Time Slot following its falling edge (Short Frame Delayed Timing).
19 IO0/GR2 DIO/DI
MCU control mode: IO0.
Slic control I/O pin #0. Can be programmed as input or output via DIR register.
Depending on content of CONF register can be a static input/output or a dynamic
input/output synchronized with the CSn
output signals controlling the SLICs.
Pin-strap control mode: GR2.
Receive gain programming channel 2:
1: Receive gain = -0.8 dB
0: Rec. gain = -4.3 dB
20 IO1/PD2 DIO/DI
MCU control mode: IO1.
Slic control I/O pin #1. (see IO0 description).
Pin-strap control mode: PD2.
Power Down command channel 2:
1: Channel 2 Codec is in power down.
(equivalent to CONF reg bit2 = 1)
0: Channel 2 Codec is in power up.
(equivalent to CONF reg. bit2 = 0)
21 IO2/GR3 DIO/DI
MCU control mode: IO2.
Slic control I/O pin #2. (see IO0 description)
Pin-strap control mode: GR3.
Receive gain programming channel 3. (see GR2 description)
22 IO3/PD3 DIO/DI
MCU control mode: IO3.
Slic control I/O pin #3. (see IO0 description).
Pin-strap control mode: PD3.
Power down command channel 3. (see PD2 description)
23 IO4/FS1 DIO/DI
MCU control mode: IO4
Slic control I/O pin #4. (see IO0 description).
Pin-strap control mode: FS1.
Frame sync. pulse of channel #1. One MCLK cycle long, starts PCM data transfer in
the time slot following its falling edge (short frame delayed timing).
24 IO5/FS2 DIO/DI
MCU control mode: IO4.
Slic control I/O pin #5. (see IO0 description).
Pin-strap control mode: FS2.
Frame sync. pulse of channel #1. One MCLK cycle long, starts PCM data transfer in
the time slot following its falling edge (short frame delayed timing).
Table 3. Pin description (continued)
N. Name Type Function
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51

STLC5046

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Buy STLC5046
Manufacturer:
STMicroelectronics
Description:
Interface - CODECs Prog 4-Ch CODEC/Filt
Lifecycle:
New from this manufacturer.
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