STLC5046 Registers addresses
Doc ID 7052 Rev 5 19/51
3.1 Registers description
3.1.1 Configuration register (CONF)
Addr=00h; Reset Value=3Fh
RES=0 Normal operation
RES=1 Device reset: I/0n and CSn
are all inputs, DX is H.I. (equivalent to Hw. reset).
LIN=0 A or µ Law PCM encoding
LIN=1 Linear encoding (16 bits), two’s complement.
AMU=0 µ Law selection
AMU=1 A Law selection (even bits inverted)
STA=0 CS0
to CS3 scan the four SLICs connected to the I/O control port, each CS has a
31.25µs repetition time.
STA=1; I/O are static, CS0
to CS3 are configured as generic static I/O
PD3..0=0 CODEC 3..0 is active
PD3..0=1 CODEC 3..0 is in power Down. When one codec is in Power Down the
corresponding VFRO output is forced to AGND. and the corresponding transmit time slot on
DX is set in H.I.
Pin-strap value:
3.1.2 I/O Direction register (DIR)
Addr=01h; Reset Value=00h
Addr=02h; Reset Value=X0h
IO11..0 = 0; I/O pin 11..0 is an input, data on the I/O input is written in DATAn register bit
11..0.
IO
11..0 = 1; I/O pin 11..0 is an output, data contained in DATAn register bit11..0 is transferred
to the I/O output.
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
RES LIN AMU STA PD3 PD2 PD1 PD0
RES 0 AMU 0 PD3 PD2 PD1 PD0
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
IO
7 IO6 IO5 IO4 IO3 IO2 IO1 IO0
IO11 IO10 IO9 IO8
