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STLC5046

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51
Block diagram and pin connection STLC5046
10/51 Doc ID 7052 Rev 5
62 IO6/FS3 DIO/DI
MCU control mode: IO4.
Slic control I/O pin #6. (see IO0 description).
Pin-strap control mode: FS3.
Frame sync. pulse of channel #1. One MCLK cycle long, starts PCM data transfer in
the time slot following its falling edge (short frame delayed timing).
28 CS0
/GX0 DO/DI
MCU control mode: CS0.
Slic CS control #0.
Depending on CONF reg. content can be a CS output for SLIC #0 or a static I/O.
When configured as CS output it is automatically generated by the Codec with a
repetition time of 31.25 µs. In this mode also the IO11.0 are synchronized and carry
proper data in and out synchronous with CS.
Pin-strap control mode: GX0.
Transmit gain programming channel 0:
1: Transmit gain = 0 dB
0: Transmit gain = - 3.5 dB
29 CS1
/GX1 DO/DI
MCU control mode: CS1
:
Slic CS control #1, (see CS0
description).
Pin-strap control mode: GX1.
Transmit gain programming channel 1 (see GX0 description)
53 CS2/GX2 DO/DI
MCU control mode: CS2
.
Slic CS control #2, (see CS0
description).
Pin-strap control mode: GX2.
Transmit gain programming channel 2 (see GX0 description)
52 CS3
/GX3 DO/DI
MCU control mode: CS3
.
Slic CS control #3, (see CS0 description).
Pin-strap control mode: GX3.
Transmit gain programming channel 3 (see GX0 description)
4CS
/PD1 DI/DI
MCU control mode: CS
.
Chip Select of Serial Control Bus. When this pin is low control information can be
written to or read from the device via the CI and CO pins.
Pin-strap control mode: PD1.
Power Down command channel 1. (see PD2 description).
7
CCLK/GR1
DI/DI
MCU control mode: CCLK.
Clock of Serial Control Bus. This clock shifts serial control information into or out of
CI or CO when CS input is low depending on the current instruction. CCLK may be
asynchronous with the other system clocks.
Pin-strap control mode: GR1.
Receive gain programming ch. 1, (see GR2 description).
6CI/PD0DI/DI
MCU control mode: CI.
Control Data Input of Serial Control Bus. Control data is shifted in the device when
CS
is low and clocked by CCLK.
Pin-strap control mode: PD0.
Power Down command channel 0. (see PD2 description).
Table 3. Pin description (continued)
N. Name Type Function
STLC5046 Block diagram and pin connection
Doc ID 7052 Rev 5 11/51
5 CO/GR0 DTO/DI
MCU control mode: CO.
Control Data Output of Serial Control Bus. Control data is shifted out the device
when CS
is low and clocked by CCLK. During the first 8 CCLK pulses the CO pin is
H. I., valid data are shifted out during the following 8 CCLK pulses.
Pin-strap control mode: GR0.
Receive gain programming ch. 0, (see GR2 description).
3INT
/AMU ODO/DI
MCU control mode: INT
.
Interrupt output (open drain), goes low when a data change has been detected in
the I/O pins. One mask registers allow to mask any I/O pin. Interrupt is reset when
the I/O register is read.
Pin-strap control mode: AMU.
A/µ Law selection:
AMU=0: µ Law
AMU=1: A Law, even bit inverted
Table 3. Pin description (continued)
N. Name Type Function
Functional description STLC5046
12/51 Doc ID 7052 Rev 5
2 Functional description
2.1 Power on initialization
When power is first applied it is recommended to reset the device by forcing the condition
M1.0=00, in order to clear all the internal registers.
In MCU mode M0 is set steadily Low and the device is reset by applying a negative pulse to
M1 (its operative level in MCU mode is High); same result can be obtained by writing an
High level into the control bit RES of the CONF register.
In pin-strap mode M1 is set steadily Low and the device is reset by applying a negative
pulse to M0 (its operative level in pin-strap mode is High); at the end of the Reset phase
(M0=High) the device is programmed according to the logical configuration of the control
pins.
During the reset condition all the I/On and CS_n pins are set as inputs, DX is set in high
impedance and all VFROn outputs are forced to AGND.
2.2 Power down state
Each of the four channel may be put into power down mode by setting the appropriate bit in
the CONF register or strapping to VDD the proper pin. In this mode the eventual
programmed DX channel is set in high impedance while the VFRO outputs are forced to
AGND. In pin-strap mode the value forced on the input pin is internally updated every FS
signal.
2.3 Transmit path
The analog VFXI signal through an amplifier stage is applied to a PCM converter and the
corresponding digital signal is sent to DX output.
In MCU mode, the amplifier gain can be programmed with two different values by means of
TXG Reg.: 0 dB or +3.52 dB.
A programmable gain block after the A/D conversion allows to set transmit gain in 12dB
range, with steps <0.1dB by writing proper code into GTXn register.
Setting GTXn=00h, the transmitted signal is muted, i.e. an idle PCM signal is generated on
DX.
A/µ coding Law is selected by bit5 (AMU) of CONF reg.
Setting LIN=1 (bit6 of CONF reg.) the linear coding Law is selected (16bits); in this case the
signal sent on DX will take two adjacent PCM time slots.
In Pin-strap mode, the amplifier gain is set to 0dB; only two values of Transmit gain can be
selected according to the level of GXn control input (in Pin-strap):
GXn=1 selects the gain corresponding to GTXn=FFh (0 dB)
GXn=0 selects the gain corresponding to GTXn=8Fh (-3.5 dB)
Different gain value is obtained through proper voltage divider.
A/µ coding Law is selected according to AMU pin level:
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51

STLC5046

Mfr. #:
Buy STLC5046
Manufacturer:
STMicroelectronics
Description:
Interface - CODECs Prog 4-Ch CODEC/Filt
Lifecycle:
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