XR16C864
19
REV. 2.2.0
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
2.17 Auto Xon/Xoff (Software) Flow Control
When software flow control is enabled (See Table 18), the 864 compares one or two sequential receive data
characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) match the
programmed values, the 864 will halt transmission as soon as the current character has completed
transmission. When a match occurs, the Xoff (if enabled via IER bit-5) flag will be set and the interrupt output
pin will be activated. Following a suspension due to a match of the Xoff character, the 864 will monitor the
receive data stream for a match to the Xon-1,2 character. If a match is found, the 864 will resume operation
and clear the flags (ISR bit-4).
Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0. Following reset the user
can write any Xon/Xoff value desired for software flow control. Different conditions can be set to detect Xon/
Xoff characters (See Table 18) and suspend/resume transmissions. When double 8-bit Xon/Xoff characters
are selected, the 864 compares two consecutive receive characters with two software flow control 8-bit values
(Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly. Under the above described flow control
mechanisms, flow control characters are not placed (stacked) in the user accessible RX data buffer or FIFO.
In the event that the receive buffer is overfilling and flow control needs to be executed, the 864 automatically
sends an Xoff message (when enabled) via the serial TX output to the remote modem. The 864 sends the Xoff-
1,2 characters two-character-times (= time taken to send two characters at the programmed baud rate) after
the receive FIFO crosses the programmed trigger level (for all trigger tables A-D). To clear this condition, the
864 will transmit the programmed Xon-1,2 characters as soon as receive FIFO is less than one trigger level
below the programmed trigger level (for Trigger Tables A, B, and C) or when receive FIFO is less than the
trigger level minus the hysteresis value (for Trigger Table D). This hysteresis value is the same as the Auto
RTS Hysteresis value in Table 15. Table 7 below explains this when Trigger Table-B (See Table 11) is
selected.
* After the trigger level is reached, an xoff character is sent after a short span of time (= time required to send 2
characters); for example, after 2.083ms has elapsed for 9600 baud and 10-bit word length setting.
2.18 Special Character Detect
A special character detect feature is provided to detect an 8-bit character when bit-5 is set in the Enhanced
Feature Register (EFR). When this character (Xoff2) is detected, it will be placed in the FIFO along with normal
incoming RX data.
The 864 compares each incoming receive character with Xoff-2 data. If a match exists, the received data will
be transferred to FIFO and ISR bit-4 will be set to indicate detection of special character. Although the Internal
Register Table shows Xon, Xoff Registers with eight bits of character information, the actual number of bits is
dependent on the programmed word length. Line Control Register (LCR) bits 0-1 defines the number of
character bits, i.e., either 5 bits, 6 bits, 7 bits, or 8 bits. The word length selected by LCR bits 0-1 also
determines the number of bits that will be used for the special character comparison. Bit-0 in the Xon, Xoff
Registers corresponds with the LSB bit for the receive character.
T
ABLE
7: A
UTO
X
ON
/X
OFF
(S
OFTWARE
) F
LOW
C
ONTROL
RX T
RIGGER
L
EVEL
INT P
IN
A
CTIVATION
X
OFF
C
HARACTER
(
S
) S
ENT
(
CHARACTERS
IN
RX
FIFO
)
X
ON
C
HARACTER
(
S
) S
ENT
(
CHARACTERS
IN
RX
FIFO
)
8 8 8* 0
16 16 16* 8
24 24 24* 16
28 28 28* 24
XR16C864
20
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
REV. 2.2.0
2.19 Auto RS485 Half-duplex Control
The auto RS485 half-duplex direction control changes the behavior of the transmitter when enabled by FCTR
bit-3. By default, it de-asserts OP1#/RS485 (logic 1) output following
the last stop bit of the last character that
has been transmitted. This helps in turning around the transceiver to receive the remote station’s response.
When the host is ready to transmit next polling data packet again, it only has to load data bytes to the transmit
FIFO. The transmitter automatically re-asserts OP1#/RS485 (logic 0) output prior to sending the data.
2.20 Infrared Mode
The 864 UART includes the infrared encoder and decoder compatible to the IrDA (Infrared Data Association)
version 1.0. The IrDA 1.0 standard that stipulates the infrared encoder sends out a
3/16 of a bit wide HIGH-
pulse for each “0” bit in the transmit data stream. This signal encoding reduces the on-time of the infrared LED,
hence reduces the power consumption. See
Figure 11
below.
The infrared encoder and decoder are enabled by setting MCR register bit-6 to a ‘1’. When the infrared feature
is enabled, the transmit data output, TX, idles at logic zero level. Likewise, the RX input assumes an idle level
of logic zero from a reset and power up, see Figure 11.
Typically, the wireless infrared decoder receives the input pulse from the infrared sensing diode on the RX pin.
Each time it senses a light pulse, it returns a logic 1 to the data bit stream. However, this is not true with some
infrared modules on the market which indicate a logic 0 by a light pulse. So the 864 has a provision to invert
the input polarity to accomodate this. In this case, user can enable FCTR bit-2 to invert the input signal.
F
IGURE
11. I
NFRARED
T
RANSMIT
D
ATA
E
NCODING
AND
R
ECEIVE
D
ATA
D
ECODING
Character
Data Bits
Start
Stop
0 0 0 0 0
1 1 1 1 1
Bit Time
1/16 Clock Delay
IRdecoder-1
RX Data
Receive
IR Pulse
(RX pin)
Character
Data Bits
Start
Stop
0 0 0 0 0
1 1 1 1 1
TX D ata
Transm it
IR Pulse
(TX Pin)
Bit Tim e
1/2 Bit Tim e
3/16 Bit Tim e
IrEncoder-1
XR16C864
21
REV. 2.2.0
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
2.21 Sleep Mode with Auto Wake-Up
The 864 supports low voltage system designs, hence, a sleep mode is included to reduce its power
consumption when the chip is not actively used.
All of these conditions must be satisfied for the 864 to enter sleep mode:
no interrupts pending for all four channels of the 864 (ISR bit-0 = 1)
sleep mode of all four channels are enabled (IER bit-4 = 1)
modem inputs are not toggling (MSR bits 0-3 = 0)
RX input pins are idling at a logic 1
The 864 stops its crystal oscillator to conserve power in the sleep mode. User can check the XTAL2 pin for no
clock output as an indication that the device has entered the sleep mode.
The 864 resumes normal operation by any of the following:
a receive data start bit transition (logic 1 to 0)
a data byte is loaded to the transmitter, THR or FIFO
a change of logic state on any of the modem or general purpose serial inputs: CTS#, DSR#, CD#, RI#
If the 864 is awakened by any one of the above conditions, it will return to the sleep mode automatically after
all interrupting conditions have been serviced and cleared. If the 864 is awakened by the modem inputs, a read
to the MSR is required to reset the modem inputs. In any case, the sleep mode will not be entered while an
interrupt is pending in any channel. The 864 will stay in the sleep mode of operation until it is disabled by
setting IER bit-4 to a logic 0.
If the address lines, data bus lines, IOW#, IOR#, CSA#, CSB#, CSC#, CSD# and modem input lines remain
steady when the 864 is in sleep mode, the maximum current will be in the microamp range as specified in the
DC Electrical Characteristics on page 42. If the input lines are floating or are toggling while the 864 is in sleep
mode, the current can be up to 100 times more. If any of those signals are toggling or floating, then an external
buffer would be required to keep the address, data and control lines steady to achieve the low current.
A word of caution: owing to the starting up delay of the crystal oscillator after waking up from sleep mode, the
first few receive characters may be lost. Also, make sure the RX input is idling at logic 1 or “marking” condition
during sleep mode. This may not occur when the external interface transceivers (RS-232, RS-485 or another
type) are also put to sleep mode and cannot maintain the marking” condition. To avoid this, the system design
engineer can use a 47k ohm pull-up resistor on the RX A-D inputs.

XR16C864IQ-F

Mfr. #:
Manufacturer:
MaxLinear
Description:
UART Interface IC UART
Lifecycle:
New from this manufacturer.
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