XR16C864
27
REV. 2.2.0
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
IER[2]: Receive Line Status Interrupt Enable
If any of the LSR register bits 1, 2, 3 or 4 is a logic 1, it will generate an interrupt to inform the host controller
about the error status of the current data byte in FIFO. These LSR bits generate an interrupt immediately when
the character has been received.
•
Logic 0 = Disable the receiver line status interrupt (default).
•
Logic 1 = Enable the receiver line status interrupt.
IER[3]: Modem Status Interrupt Enable
•
Logic 0 = Disable the modem status register interrupt (default).
•
Logic 1 = Enable the modem status register interrupt.
IER[4]: Sleep Mode Enable (requires EFR[4] = 1)
•
Logic 0 = Disable Sleep Mode (default).
•
Logic 1 = Enable Sleep Mode.
SEE”SLEEP MODE WITH AUTO WAKE-UP” ON PAGE 21.
IER[5]: Xoff Interrupt Enable (requires EFR[4]=1)
•
Logic 0 = Disable the software flow control, receive Xoff interrupt (default).
•
Logic 1 = Enable the software flow control, receive Xoff interrupt. See Software Flow Control section for
details.
IER[6]: RTS# Output Interrupt Enable (requires EFR[4]=1)
•
Logic 0 = Disable the RTS# interrupt (default).
•
Logic 1 = Enable the RTS# interrupt. The UART issues an interrupt when the RTS# pin makes a transition
from low to high.
IER[7]: CTS# Input Interrupt Enable (requires EFR[4]=1)
•
Logic 0 = Disable the CTS# interrupt (default).
•
Logic 1 = Enable the CTS# interrupt. The UART issues an interrupt when CTS# pin makes a transition from
low to high.
4.4 Interrupt Status Register (ISR) - Read-Only
The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the
ISR will give the user the current highest pending interrupt level to be serviced, others are queued up to be
serviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt
Source Table,
Table 10
, shows the data values (bit 0-5) for the interrupt priority levels and the interrupt sources
associated with each of these interrupt levels.
4.4.1 Interrupt Generation:
•
LSR is by any of the LSR bits 1, 2, 3 and 4.
•
RXRDY is by RX trigger level.
•
RXRDY Time-out is by a 4-char plus 12 bits delay timer.
•
TXRDY is by TX trigger level or TX FIFO empty (or transmitter empty in auto RS-485 control).
•
MSR is by any of the MSR bits 0, 1, 2 and 3.
•
Receive Xoff/Special character is by detection of a Xoff or Special character.
•
CTS# is when its transmitter toggles the input pin (from low to high) during auto CTS flow control.
•
RTS# is when its receiver toggles the output pin (from low to high) during auto RTS flow control.
