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XR16C864IQ-F

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51
XR16C864
37
REV. 2.2.0
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
4.13 Baud Rate Generator Registers (DLL and DLM) - Read/Write
The concatenation of the contents of DLM and DLL gives the 16-bit divisor value which is used to calculate the
baud rate:
•
Baud Rate = (Clock Frequency / 16) / Divisor
See MCR bit-7 and the baud rate table also.
4.14 Device Identification Register (DVID) - Read Only
This register contains the device ID (0x14 for XR16C864). Prior to reading this register, DLL and DLM should
be set to 0x00.
4.15 Device Revision Register (DREV) - Read Only
This register contains the device revision information. For example, 0x01 means revision A. Prior to reading
this register, DLL and DLM should be set to 0x00.
4.16 Trigger Level (TRG) - Write-Only
User Programmable Transmit/Receive Trigger Level Register.
TRG[7:0]: Trigger Level Register
These bits are used to program desired trigger levels when trigger Table-D is selected. FCTR bit-7 selects
between programming the RX Trigger Level (a logic 0) and the TX Trigger Level (a logic 1).
4.17 FIFO Data Count Register (FC) - Read-Only
This register is accessible when LCR = 0xBF. Note that this register is not identical to the FIFO Level Count
Register which is located in the general register set when FCTR bit-6 = 1 (Scratchpad Register Swap). It is
suggested to read the FIFO Level Count Register at the Scratchpad Register location when FCTR bit-6 = 1.
See
Table 14
.
FC[7:0]: FIFO Data Count Register
Transmit/Receive FIFO Count. Number of characters in Transmit (FCTR[7] = 1) or Receive FIFO (FCTR[7] =
0) can be read via this register.
4.18 Feature Control Register (FCTR) - Read/Write
This register controls the XR16C864 new functions that are not available in ST16C554 or ST16C654.
FCTR[1:0]: RTS Hysteresis
User selectable RTS# hysteresis levels for hardware flow control application. After reset, these bits are set to
“0” to select the next trigger level for hardware flow control. See
Table 15
for more details.
FCTR[2]: IrDA RX Inversion
•
Logic 0 = Select RX input as encoded IrDA data (Idle state will be logic 0).
•
Logic 1 = Select RX input as inverted encoded IrDA data (Idle state will be logic 1).
FCTR[3]: Auto RS-485 Direction Control
•
Logic 0 = OP1# can be used as a general purpose output and can be controlled via MCR bit-2.
•
Logic 1 = OP1# is used as the Auto RS-485 half-duplex direction control output. The TX Ready Interrupt
behavior also changes. See
Table 3
.
XR16C864
38
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
REV. 2.2.0
FCTR[5:4]: Transmit/Receive Trigger Table Select
See
Table 11
for more details.
FCTR[6]: Scratchpad Swap
•
Logic 0 = Scratch Pad register is selected as general read and write register. ST16C550 compatible mode.
•
Logic 1 = FIFO Count register (Read-Only), Enhanced Mode Select Register (Write-Only). Number of
characters in transmit or receive holding register can be read via scratch pad register when this bit is set.
Enhanced Mode Select Register is selected when it is written into.
FCTR[7]: Programmable Trigger Register Select
•
Logic 0 = Registers TRG and FC selected for RX.
•
Logic 1 = Registers TRG and FC selected for TX.
4.19 Enhanced Feature Register (EFR) - Read/Write
Enhanced features are enabled or disabled using this register. Bit 0-3 provide single or dual consecutive
character software flow control selection (see
Table 18
). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes
are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that
whenever changing the TX or RX flow control bits, always reset all bits back to logic 0 (disable) before
programming a new setting.
T
ABLE
17: T
RIGGER
T
ABLE
S
ELECT
FCTR
B
IT
-5
FCTR
B
IT
-4
T
ABLE
0 0 Table-A (TX/RX)
0 1 Table-B (TX/RX)
1 0 Table-C (TX/RX)
1 1 Table-D (TX/RX)
XR16C864
39
REV. 2.2.0
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
EFR[3:0]: Software Flow Control Select
Single character and dual sequential characters software flow control is supported. Combinations of software
flow control can be selected by programming these bits.
EFR[4]: Enhanced Function Bits Enable
Enhanced function control bit. This bit enables IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR bits 5-7 to be
modified. After modifying any enhanced bits, EFR bit-4 can be set to a logic 0 to latch the new values. This
feature prevents legacy software from altering or overwriting the enhanced functions once set. Normally, it is
recommended to leave it enabled, logic 1.
•
Logic 0 = modification disable/latch enhanced features. IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR
bits 5-7 are saved to retain the user settings. After a reset, the IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and
MCR bits 5-7are set to a logic 0 to be compatible with ST16C550 mode (default).
•
Logic 1 = Enables the above-mentioned register bits to be modified by the user.
EFR[5]: Special Character Detect Enable
•
Logic 0 = Special Character Detect Disabled (default).
•
Logic 1 = Special Character Detect Enabled. The UART compares each incoming receive character with
data in Xoff-2 register. If a match exists, the receive data will be transferred to FIFO and ISR bit-4 will be set
to indicate detection of the special character. Bit-0 corresponds with the LSB bit of the receive character. If
flow control is set for comparing Xon1, Xoff1 (EFR [1:0]= ‘10’) then flow control and special character work
normally. However, if flow control is set for comparing Xon2, Xoff2 (EFR[1:0]= ‘01’) then flow control works
normally, but Xoff2 will not go to the FIFO, and will generate an Xoff interrupt and a special character
interrupt, if enabled via IER bit-5.
T
ABLE
18: S
OFTWARE
F
LOW
C
ONTROL
F
UNCTIONS
EFR
BIT
-3
C
ONT
-3
EFR
BIT
-2
C
ONT
-2
EFR
BIT
-1
C
ONT
-1
EFR
BIT
-0
C
ONT
-0
T
RANSMIT
AND
R
ECEIVE
S
OFTWARE
F
LOW
C
ONTROL
0 0 0 0 No TX and RX flow control (default and reset)
0 0 X X No transmit flow control
1 0 X X Transmit Xon1, Xoff1
0 1 X X Transmit Xon2, Xoff2
1 1 X X Transmit Xon1 and Xon2, Xoff1 and Xoff2
X X 0 0 No receive flow control
X X 1 0 Receiver compares Xon1, Xoff1
X X 0 1 Receiver compares Xon2, Xoff2
1 0 1 1 Transmit Xon1, Xoff1
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
0 1 1 1 Transmit Xon2, Xoff2
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
1 1 1 1 Transmit Xon1 and Xon2, Xoff1 and Xoff2,
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
0 0 1 1 No transmit flow control,
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51

XR16C864IQ-F

Mfr. #:
Buy XR16C864IQ-F
Manufacturer:
MaxLinear
Description:
UART Interface IC UART
Lifecycle:
New from this manufacturer.
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