MT9V032
www.onsemi.com
12
SERIAL BUS DESCRIPTION
Registers are written to and read from the MT9V032
through the two−wire serial interface bus. The MT9V032 is
a serial interface slave with four possible IDs (0x90, 0x98,
0xB0,and 0xB8) determined by the S_CTRL_ADR0 and
S_CTRL_ADR1 input pins. Data is transferred into the
MT9V032 and out through the serial data (S
DATA) line. The
S
DATA line is pulled up to VDD off−chip by a 1.5KW resistor.
Either the slave or master device can pull the S
DATA line
down—the serial interface protocol determines which
device is allowed to pull the SDATA line down at any given
time. The registers are 16−bit wide, and can be accessed
through 16− or 8−bit two−wire serial interface sequences.
Protocol
The two−wire serial interface defines several different
transmission codes, as follows:
• a start bit
• the slave device 8−bit address
• a(n) (no) acknowledge bit
• an 8−bit message
• a stop bit
Sequence
A typical read or write sequence begins by the master
sending a start bit. After the start bit, the master sends the
slave device’s 8−bit address. The last bit of the address
determines if the request is a read or a write, where a “0”
indicates a write and a “1” indicates a read. The slave device
acknowledges its address by sending an acknowledge bit
back to the master.
If the request was a write, the master then transfers the
8−bit register address to which a write should take place. The
slave sends an acknowledge bit to indicate that the register
address has been received. The master then transfers the data
8 bits at a time, with the slave sending an acknowledge bit
after each 8 bits. The MT9V032 uses 16−bit data for its
internal registers, thus requiring two 8−bit transfers to write
to one register. After 16 bits are transferred, the register
address is automatically incremented, so that the next 16 bits
are written to the next register address. The master stops
writing by sending a start or stop bit.
A typical read sequence is executed as follows. First the
master sends the write mode slave address and 8−bit register
address, just as in the write request. The master then sends
a start bit and the read mode slave address. The master then
clocks out the register data 8 bits at a time. The master sends
an acknowledge bit after each 8−bit transfer. The register
address is auto−incremented after every 16 bits is
transferred. The data transfer is stopped when the master
sends a no−acknowledge bit. The MT9V032 allows for 8−bit
data transfers through the two−wire serial interface by
writing (or reading) the most significant 8 bits to the register
and then writing (or reading) the least significant 8 bits to
R0xF0 (240).
Bus Idle State
The bus is idle when both the data and clock lines are
HIGH. Control of the bus is initiated with a start bit, and the
bus is released with a stop bit. Only the master can generate
the start and stop bits.
Start Bit
The start bit is defined as a HIGH−to−LOW transition of
the data line while the clock line is HIGH.
Stop Bit
The stop bit is defined as a LOW−to−HIGH transition of
the data line while the clock line is HIGH.
Slave Address
The 8−bit address of a two−wire serial interface device
consists of 7 bits of address and 1 bit of direction. A “0” in
the LSB of the address indicates write mode, and a “1”
indicates read mode. As indicated above, the MT9V032
allows four possible slave addresses determined by the two
input pins, S_CTRL_ADR0 and S_CTRL_ADR1.
