MT9V032
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26
Table 8. REGISTER DESCRIPTIONS
0X74 (116) PIXEL CLOCK, FRAME AND LINE VALID CONTROL
4
Invert Pixel Clock Invert pixel clock. When set, LINE_VALID, FRAME_VALID,
and D
OUT is set up to the rising edge of pixel clock, PIXCLK.
When clear, they are set up to the falling edge of PIXCLK.
0 Y 0, 1 W
0X7F (127) DIGITAL TEST PATTERN
9:0
Two−wire Serial Inter-
face Test Data
The 10−bit test data in this register is used in place of the
data from the sensor. The data is inserted at the beginning
of the digital signal processing. Both test enable (bit 13) and
use two−wire serial interface (bit 10) must be set.
0 N 0–1023 W
10 Use Two−wire Serial In-
terface Test Data
0 = Use Gray Shade Test Pattern as test data.
1 = Use Two−wire Serial Interface Test Data (bits 9:0) as
test data.
0 N 0, 1 W
12:11 Gray Shade Test Pat-
tern
0 = None.
1 = Vertical Shades.
2 = Horizontal Shades.
3 = Diagonal Shade.
When bits (12:11)
! 0, the MT9V032 generates a gray
shaded test pattern to be used as digital test data. Ineffec-
tive when Use Two−wire Serial Interface Test Data (bit 10)
is set.
0 N 0–3 W
13 Test Enable Enable the use of test data/gray shaded test pattern in the
signal chain. The data is inserted instead of data from the
ADCs.
Set R0x70 bit 5 = 0 when using this mode. If R0x70 bit 5 =
1, the row−wise correction algorithm processes the test data
values and the result is not accurate.
0 Y 0, 1 W
14 Flip Two−Wire Serial In-
terface Test Data
Use only when two−wire serial interface test data (bit 10) is
set. When set, the two−wire serial interface test data (bits
9:0) is used in place of the data from ADC/memory on odd
columns, while complement of the two−wire serial interface
test data is used on even columns.
0 N 0, 1 W
0X80 (128) − 0X98 (152) TILED DIGITAL GAIN
3:0
Tile Gain Tile Digital Gain = Bits (3:0) x 0.25. See “Gain Settings” for
additional information on digital gain.
4 Y 1–15 W
7:4 Sample Weight To indicate the weight of individual tile used in the automatic
gain/exposure control algorithm.
F
(15)
Y 0–15 W
Refer to Figure 25 for R0x99 (153) − R0xA4 (164).
0X99 (153) DIGITAL TILE COORDINATE 1 − X−DIRECTION
9:0
X
0/5
The starting x−coordinate of digital tiles X0_*. 0 Y 0–752 W
0X9A (154) DIGITAL TILE COORDINATE 2 − X−DIRECTION
9:0
X
1/5
The starting x−coordinate of digital tiles X1_*. 096
(150)
Y 0–752 W
0X9B (155) DIGITAL TILE COORDINATE 3 − X−DIRECTION
9:0
X
2/5
The starting x−coordinate of digital tiles X2_*. 12C
(300)
Y 0–752 W
0X9C (156) DIGITAL TILE COORDINATE 4 − X−DIRECTION
9:0
X
3/5
The starting x−coordinate of digital tiles X3_*. 1C2
(450)
Y 0–752 W
0X9D (157) DIGITAL TILE COORDINATE 5 − X−DIRECTION
9:0
X
4/5
The starting x−coordinate of digital tiles X4_*. 258
(600)
Y 0–752 W
0X9E (158) DIGITAL TILE COORDINATE 6 − X−DIRECTION
9:0
X
5/5
The ending x−coordinate of digital tiles X4_*. 2F0
(752)
Y 0–752 W
