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MT9V032C12STMH-GEVB

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P61
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Table 10. LVDS PACKET FORMAT IN STEREOSCOPY MODE (Stereoscopy Mode Bit Asserted)
18−bit Packet Function
Bit[0] 1’b1 (Start bit)
Bit[1] Master Sensor Pixel Data [2]
Bit[2] Master Sensor Pixel Data [3]
Bit[3] Master Sensor Pixel Data [4]
Bit[4] Master Sensor Pixel Data [5]
Bit[5] Master Sensor Pixel Data [6]
Bit[6] Master Sensor Pixel Data [7]
Bit[7] Master Sensor Pixel Data [8]
Bit[8] Master Sensor Pixel Data [9]
Bit[9] Slave Sensor Pixel Data [2]
Bit[10] Slave Sensor Pixel Data [3]
Bit[11] Slave Sensor Pixel Data [4]
Bit[12] Slave Sensor Pixel Data [5]
Bit[13] Slave Sensor Pixel Data [6]
Bit[14] Slave Sensor Pixel Data [7]
Bit[15] Slave Sensor Pixel Data [8]
Bit[16] Slave Sensor Pixel Data [9]
Bit[17] 1’b0 (Stop bit)
Control signals LINE_VALID and FRAME_VALID can
be reconstructed from their respective preceding and
succeeding flags that are always embedded within the pixel
data in the form of reserved words.
Table 11. RESERVED WORDS IN THE PIXEL DATA STREAM
Pixel Data Reserved Word Flag
0 Precedes frame valid assertion
1 Precedes line valid assertion
2 Succeeds line valid de−assertion
3 Succeeds frame valid de−assertion
When LVDS mode is enabled along with column binning
(bin 2 or bin 4, R0x0D[3:2]), the packet size remains the
same but the serial pixel data stream repeats itself depending
on whether 2X or 4X binning is set:
• For bin 2, LVDS outputs double the expected data
(pixel 0,0 is output twice in sequence, followed by pixel
0,1 twice, . . .).
• For bin 4, LVDS outputs 4 times the expected data
(pixel 0,0 is output 4 times in sequence followed by
pixel 0,1 times 4, . . .).
The receiving hardware will need to undersample the
output stream getting data either every 2 clocks (bin 2) or
every 4 (bin 4) clocks.
If the sensor provides a pixel whose value is 0,1, 2, or 3
(that is, the same as a reserved word) then the outgoing serial
pixel value is switched to 4
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ELECTRICAL SPECIFICATIONS
Table 12. DC ELECTRICAL CHARACTERISTICS (VPWR = 3.3V +0.3V; T
A
= Ambient = 25°C)
Symbol
Definition Condition Minimum
Typi
cal
Maximum Unit
VIH Input high voltage VPWR − 0.5 – VPWR + 0.3 V
VIL Input low voltage –0.3 – 0.8 V
IIN Input leakage current
No pull−up resistor;
V
IN = VPWR or VGND
–15.0
– 15.0
mA
VOH Output high voltage IOH = –4.0mA VPWR −0.7 – – V
VOL Output low voltage IOL = 4.0mA – – 0.3 V
IOH Output high current VOH = VDD − 0.7 –9.0 – – mA
IOL Output low current VOL = 0.7 – – 9.0 mA
VAA Analog power supply Default settings 3.0 3.3 3.6 V
IPWRA Analog supply current Default settings – 35.0 60.0 mA
VDD Digital power supply Default settings 3.0 3.3 3.6 V
IPWRD Digital supply current
Default settings, CLOAD= 10pF
–
35.0 60 mA
VAAPIX
Pixel array power sup-
ply
Default settings
3.0
3.3 3.6 V
IPIX Pixel supply current Default settings 0.5
1.4 3.0 mA
VLVDS LVDS power supply Default settings 3.0 3.3 3.6 V
ILVDS LVDS supply current Default settings 11.0 13.0 15.0 mA
IPWRA Standby
Analog standby supply
current
STDBY = VDD
2
3 4
mA
IPWRD Standby
Clock Off
Digital standby supply
current with clock off
STDBY = VDD, CLKIN = 0 MHz
1
2 4
mA
IPWRD Standby
Clock On
Digital standby supply
current with clock on
STDBY= VDD, CLKIN = 27 MHz
–
1.05 – mA
LVDS DRIVER DC SPECIFICATIONS
|V
OD|
Output differential volt-
age
RLOAD = 100
W ± 1%
250
– 400 mV
|DVOD|
Change in VOD between
complementary output
states
–
– 50 mV
VOS Output offset voltage
1.0
1.2 1.4 mV
DVOS
Change in VOS between
complementary output
states
–
– 35 mV
IOS
Output current when
driver shorted to ground
±10 ±12
mA
IOZ
Output current when
driver is tri−state
±1 ±10
mA
LVDS RECEIVER DC SPECIFICATIONS
VIDTH+
Input differential
| VGPD| < 925mV
–100
– 100 mV
Iin Input current
–
–
±20
mA
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Table 13. ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter Minimum Maximum Unit
VSUPPLY Power supply voltage (all supplies) –0.3 4.5 V
ISUPPLY Total power supply current – 200 mA
IGND Total ground current – 200 mA
VIN DC input voltage –0.3 VDD + 0.3 V
VOUT DC output voltage –0.3 VDD + 0.3 V
TSTG
1
Storage temperature –40 +125 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
5. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
Table 14.
AC ELECTRICAL CHARACTERISTICS (VPWR = 3.3V ±0.3V; T
A
= Ambient = 25°C; Output Load = 10pF)
Definition
Symbol Condition Min Typ Max Unit
SYSCLK Input clock frequency Note 1 13.0 26.6 27.0 MHz
Clock duty cycle 45.0 50.0 55.0 %
t
R
Input clock rise time
1 2 5 ns
t
F
Input clock fall time
1 2 5 ns
tPLHP
SYSCLK to PIXCLK
propagation delay
CLOAD = 10pF
3 7 11 ns
tPD
PIXCLK to valid DOUT(9:0)
propagation delay
CLOAD = 10pF
–2 0 2 ns
tSD Data setup time 14 16 – ns
tHD Data hold time 14 16 – ns
tPFLR
PIXCLK to LINE_VALID
propagation delay
CLOAD = 10pF
–2 0 2 ns
tPFLF
PIXCLK to FRAME_VALID
propagation delay
CLOAD = 10pF
–2 0 2 ns
6. The frequency range specified applies only to the parallel output mode of operation.
Propagation Delays for PIXCLK and Data Out Signals
The pixel clock is inverted and delayed relative to the
master clock. The relative delay from the master clock
(SYSCLK) rising edge to both the pixel clock (PIXCLK)
falling edge and the data output transition is typically 7ns.
Note that the falling edge of the pixel clock occurs at
approximately the same time as the data output transitions.
See Table 14 for data setup and hold times.
Propagation Delays for FRAME_VALID and
LINE_VALID Signals
The LINE_VALID and FRAME_VALID signals change
on the same rising master clock edge as the data output. The
LINE_VALID goes HIGH on the same rising master clock
edge as the output of the first valid pixel’s data and returns
LOW on the same master clock rising edge as the end of the
output of the last valid pixel’s data.
As shown in the Output Data Timing, FRAME_VALID
goes HIGH 143 pixel clocks before the first
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P61

MT9V032C12STMH-GEVB

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Buy MT9V032C12STMH-GEVB
Manufacturer:
ON Semiconductor
Description:
Optical Sensor Development Tools WVGA 1/3" GS CIS HB
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