MT9V032
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48
stand−alone sensor is able to reproduce the standard parallel
output (8−bit pixel data, LINE_VALID, FRAME_VALID
and PIXCLK). The deserializer attached to a stereoscopic
sensor is able to reproduce 8−bit pixel data from each sensor
(with embedded LINE_VALID and FRAME_VALID) and
pixel−clk. An additional (simple) piece of logic is required
to extract LINE_VALID and FRAME_VALID from the
8−bit pixel data. Irrespective of the mode
(stereoscopy/stand−alone), LINE_VALID and
FRAME_VALID are always embedded in the pixel data.
In stereoscopic mode, the two sensors run in lock−step,
implying all state machines are in the same state at any given
time. This is ensured by the sensor−pair getting their
sys−clks and sys−resets in the same instance. Configuration
writes through the two−wire serial interface are done in such
a way that both sensors can get their configuration updates
at once. The inter−sensor serial link is designed in such a
way that once the slave PLL locks and the data−dly,
shft−clk−dly and stream−latency−sel are configured, the
master sensor streams good stereo content irrespective of
any variation voltage and/or temperature as long as it is
within specification. The configuration values of data−dly,
shft−clk−dly and stream−latency−sel are either
predetermined from the board layout or can be empirically
determined by reading back the stereo−error flag. This flag
gets asserted when the two sensor streams are not in sync
when merged. The combo_reg is used for out−of−sync
diagnosis.
Figure 34. Serial Output Format for 6x2 Frame
Internal
PIXCLK
Internal
Parallel
Data
Internal
Line_Valid
Internal
Frame_Valid
External
Serial
Data Out
NOTES: 1. External pixel values of 0, 1, 2, 3, are reserved (they only convey control information).
Any raw pixel of value 0, 1, 2 and 3 will be substituted with 4.
2. The external pixel sequence 1023, 0 1023 is a reserved sequence (conveys control
information). Any raw pixel sequence of 1023, 0, 1023 will be substituted with 1023, 4, 1023.
P42P41 P43 P44 P45 P46 P52 P53 P54 P56
P55
P51
1023 0 1023 1 P41 P42 P43 P44 P45 P46 2 1 P51 P52 P53 P54 P55 P56 3
LVDS Output Format
In stand−alone mode, the packet size is 12 bits (2 frame
bits and 10 payload bits); 10−bit pixels or 8−bit pixels can be
selected. In 8−bit pixel mode (R0xB6[0] = 0), the packet
consists of a start bit, 8−bit pixel data (with sync codes), the
line valid bit, the frame valid bit and the stop bit. For 10−bit
pixel mode (R0xB6[0] = 1), the packet consists of a start bit,
10−bit pixel data, and the stop bit.
Table 9. LVDS PACKET FORMAT IN STAND−ALONE MODE (Stereoscopy Mode Bit De−Asserted)
12 Bit Packet
Use_10−bit_pixels Bit De−Asserted
(8−Bit Mode)
Use_10−bit_pixels Bit Asserted
(10−Bit Mode)
Bit[0] 1’b1(Start bit) 1’b1(Start bit)
Bit[1] PixelData[2] PixelData[0]
Bit[2] PixelData[3] PixelData[1]
Bit[3] PixelData[4] PixelData[2]
Bit[4] PixelData[5] PixelData[3]
Bit[5] PixelData[6] PixelData[4]
Bit[6] PixelData[7] PixelData[5]
Bit[7] PixelData[8] PixelData[6]
Bit[8] PixelData[9] PixelData[7]
Bit[9] Line_Valid PixelData[8]
Bit[10] Frame_Valid PixelData[9]
Bit[11] 1’b0(Stop bit) 1’b0(Stop bit)
In stereoscopic mode (see Figure 47), the packet size is 18
bits (2 frame bits and 16 payload bits). The packet consists
of a start bit, the master pixel byte (with sync codes), the
slave byte (with sync codes), and the stop bit.)
