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Table 6. SLAVE ADDRESS MODES
{S_CTRL_ADR1, S_CTRL_ADR0} Slave Address Write/Read Mode
00 0x90 Write
0x91 Read
01 0x98 Write
0x99 Read
10 0xB0 Write
0xB1 Read
11 0xB8 Write
0xB9 Read
Data Bit Transfer
One data bit is transferred during each clock pulse. The
twowire serial interface clock pulse is provided by the
master. The data must be stable during the HIGH period of
the serial clock—it can only change when the twowire
serial interface clock is LOW. Data is transferred 8 bits at a
time, followed by an acknowledge bit.
Acknowledge Bit
The master generates the acknowledge clock pulse. The
transmitter (which is the master when writing, or the slave
when reading) releases the data line, and the receiver
indicates an acknowledge bit by pulling the data line LOW
during the acknowledge clock pulse.
NoAcknowledge Bit
The noacknowledge bit is generated when the data line
is not pulled down by the receiver during the acknowledge
clock pulse. A noacknowledge bit is used to terminate a
read sequence.
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TWOWIRE SERIAL INTERFACE SAMPLE READ AND WRITE SEQUENCES
16Bit Write Sequence
A typical write sequence for writing 16 bits to a register
is shown in Figure 9. A start bit given by the master, followed
by the write address, starts the sequence. The image sensor
then gives an acknowledge bit and expects the register
address to come first, followed by the 16bit data. After each
8bit word is sent, the image sensor gives an acknowledge
bit. All 16 bits must be written before the register is updated.
After 16 bits are transferred, the register address is
automatically incremented, so that the next 16 bits are
written to the next register. The master stops writing by
sending a start or stop bit.
Figure 9. Timing Diagram Showing a Write to R0x09 with Value 0x0284
SCLK
START ACK
0xB8 ADDR 0000 0010
R0x09
ACK ACK ACK
STOP
1000 0100
S
DATA
16Bit Read Sequence
A typical read sequence is shown in Figure 10. First the
master has to write the register address, as in a write
sequence. Then a start bit and the read address specify that
a read is about to happen from the register. The master then
clocks out the register data 8 bits at a time. The master sends
an acknowledge bit after each 8bit transfer. The register
address is autoincremented after every 16 bits is
transferred. The data transfer is stopped when the master
sends a noacknowledge bit.
Figure 10. Timing Diagram Showing a Read from R0x09; Returned Value 0x0284
SCLK
START ACK
0xB8 ADDR 0xB9 ADDR 0000 0010
R0x09
ACK ACK ACK
STOP
1000 0100
NACK
S
DATA
8Bit Write Sequence
To be able to write 1 byte at a time to the register, a special
register address is added. The 8bit write is done by first
writing the upper 8 bits to the desired register and then
writing the lower 8 bits to the special register address
(R0xF0). The register is not updated until all 16 bits have
been written. It is not possible to just update half of a register.
In Figure 11, a typical sequence for 8bit writing is shown.
The second byte is written to the special register (R0xF0).
Figure 11. Timing Diagram Showing a Bytewise Write to R0x09 with Value 0x0284
STOP
ACKSTART
0xB8 ADDR
ACK
SCLK
ACKACKACKACK
R0x09
0xB8 ADDR
0000 0010 1000 0100
START
S
DATA
R0xF0
8Bit Read Sequence
To read one byte at a time the same special register address
is used for the lower byte. The upper 8 bits are read from the
desired register. By following this with a read from the
special register (R0xF1) the lower 8 bits are accessed
(Figure 12). The master sets the noacknowledge bits
shown.
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Figure 12. Timing Diagram Showing a Bytewise Read from R0x09; Returned Value 0x0284
START
0xB9 ADDR
SCLK
STOP
ACKACKACK
R0x09
START
0xB8 ADDR
0000 0010
START
0xB9 ADDR
SCLK
NACKACKACKACKSTART
0xB8 ADDR 1000 0100
S
DATA
S
DATA
NACK
R0xF0
Register Lock
Included in the MT9V032 is a register lock (R0xFE)
feature that can be used as a solution to reduce the
probability of an inadvertent noisetriggered twowire
serial interface write to the sensor. All registers (or read
mode register—register 13 only) can be locked.
At powerup, the register lock defaults to a value of
0xBEEF, which implies that all registers are unlocked and
any twowire serial interface writes to the register get
committed.
Lock All Registers
If a unique pattern (0xDEAD) to R0xFE is programmed,
any subsequent twowire serial interface writes to registers
(except R0xFE) are NOT committed. Alternatively, if the
user writes a 0xBEEF to the register lock register, all
registers are unlocked and any subsequent twowire serial
interface writes to the register are committed.
Lock Read More Register Only (R0x0D)
If a unique pattern (0xDEAF) to R0xFE is programmed,
any subsequent twowire serial interface writes to register
13 are NOT committed. Alternatively, if the user writes a
0xBEEF to register lock register, register 13 is unlocked and
any subsequent twowire serial interface writes to this
register are committed.

MT9V032C12STMH-GEVB

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Optical Sensor Development Tools WVGA 1/3" GS CIS HB
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