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MT9V032C12STMH-GEVB

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P61
MT9V032
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28
Table 8. REGISTER DESCRIPTIONS
0XAB (171) AGC LOW PASS FILTER
1:0
Gain LPF This value plays a role in determining the increment/decre-
ment size of gain value from frame to frame. If current bin !
0 (R0xBC)
When Gain LPF = 0
Actual new gain = Calculated new gain
When Exp LPF = 1
if |(Calculated new gain − current gain) | > (current gain/4),
Actual new gain = Calculated new gain, otherwise
Actual new gain = Current exp+ (calculated new gain/2)
When Exp LPF = 2:
if |(Calculated new gain − current gain) | > (current gain /4),
Actual new gain = Calculated new gain, otherwise
Actual new gain = Current gain+ (calculated new gain/4).
2 Y 0–2 W
0XAF (175) AGC/AEC ENABLE
0
AEC Enable 0 = Disable Automatic Exposure Control
1 = Enable Automatic Exposure Control
1
Y 0, 1 W
1 AGC Enable 0 = Disable Automatic Gain Control.
1 = Enable Automatic Gain Control.
1
Y 0, 1 W
0XB0 (176) AGC/AEC PIXEL COUNT
15−0
Pixel Count The number of pixel used for the AEC/AGC histogram. ABE0
(44,00)
Y 0–65535 W
0XB1 (177) LVDS MASTER CONTROL
0
PLL Bypass 0 = Internal shift−CLK is driven by PLL.
1 = Internal shift−CLK is sourced from the LVDS_BY-
PASS_CLK.
0 Y 0, 1 W
1 LVDS Power−down 0 = Normal operation.
1 = Power−down LVDS block.
1 Y 0, 1 W
2 PLL Test Mode 0 = Normal operation.
1 = The PLL output frequency is equal to the system clock
frequency (26.6 MHz).
0 Y 0, 1 W
3 LVDS Test Mode 0 = Normal operation.
1 = The SER_DATAOUT_P drives a square wave in both
stereo and stand−alone modes). In stereo mode, ensure
that SER_DATAIN_P is logic “0.”
0 Y 0, 1 W
0XB2 (178) LVDS SHIFT CLOCK CONTROL
2:0
Shift−clk Delay Element
Select
The amount of shift−CLK delay that minimizes inter−sensor
skew.
0 Y 0–7 W
4 LVDS Receiver Power−
down
When set, LVDS receiver is disabled. 1 Y 0, 1 W
0XB3 (179) LVDS DATA CONTROL
2:0
Data Delay Element
Select
The amount of data delay that minimizes inter−sensor skew. 0 Y 0–7 W
4 LVDS Driver Power−
down
When set, data LVDS driver is disabled. 1 Y 0, 1 W
0XB4 (180) LVDS LATENCY
1:0
Stream Latency Select The amount of delay so that the two streams are in sync. 0 Y 0–3 W
0XB5 (181) LVDS INTERNAL SYNC
0
LVDS Internal Sync En-
able
When set, the MT9V032 generates sync pattern (data with
all zeros except start bit) on LVDS_SER_DATA_OUT.
0 Y 0, 1 W
0XB6 (182) LVDS PAYLOAD CONTROL
MT9V032
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29
Table 8. REGISTER DESCRIPTIONS
0XB6 (182) LVDS PAYLOAD CONTROL
0
Use 10−bit Pixel Enable When set, all 10 pixel data bits are output in stand−alone
mode. Control signals are embedded. If clear, 8 bits of pixel
data are output with 2 control bits. See “LVDS Output For-
mat” for additional information.
0 Y 0, 1 W
0XB7 (183) STEREOSCOPY ERROR CONTROL
0 Enable Stereo Error
Detect
Set this bit to enable stereo error detect mechanism. 0 Y 0, 1 W
1 Enable Stick Stereo Er-
ror Flag
When set, the stereo error flag remains asserted once an
error is detected unless clear stereo error flag (bit 2) is set.
0 Y 0, 1 W
2 Clear Stereo Error Flag Set this bit to clear the stereoscopy error flag (R0xB8
returns to logic 0).
0 Y 0, 1 W
0XB8 (184) STEREOSCOPY ERROR FLAG
0
Stereoscopy Error Flag Stereoscopy error status flag. It is also directly connected to
the ERROR output pin.
R
0XB9 (185) LVDS DATA OUTPUT
15:0
Combo Reg This 16−bit value contains both 8−bit pixel values from both
stereoscopic master and slave sensors. It can be used in
diagnosis to determine how well in sync the two sensors
are. Captures the state when master sensor has issued
a reserved byte and slave has not.
Note: This register should be read from the stereoscopic
master sensor only.
R
0XBA (186) AGC GAIN OUTPUT
6:0
AGC Gain Status register to report the current gain value obtained
from the AGC algorithm.
10
(16)
R
0XBB (187) AEC EXPOSURE OUTPUT
15:0
AEC Exposure Status register to report the current exposure value obtained
from the AEC Algorithm.
00C8
(200)
R
0XBC (188) AGC/AEC CURRENT BIN
5:0
Current Bin Status register to report the current bin of the histogram. R
0XBD (189) MAXIMUM TOTAL SHUTTER WIDTH
15:0
Maximum Total Shutter
Width
This register is used by the automatic exposure control
(AEC) as the upper threshold of exposure. This ensures the
new calibrated integration value does not exceed that which
the MT9V032 supports.
01E0
(480)
Y 1–2047 W
0XBE (190) AGC/AEC BIN DIFFERENCE THRESHOLD
7:0
Bin Difference Thresh-
old
This register is used by the AEC only when exposure reach-
es its minimum value of 1. If the difference between desired
bin (R0xA5) and current bin (R0xBC) is larger than the
threshold, the exposure is increased.
14
(20)
Y 0–63 W
0XBF (191) FIELD VERTICAL BLANK
8:0
Field Vertical Blank The number of blank rows between odd and even fields.
Note: For interlaced (both field) mode only. See R0x07[2:0].
16
(22)
Y 0–255 W
0XC0 (192) MONITOR MODE CAPTURE CONTROL
7:0
Image Capture Numb The number of frames to be captured during the wake−up
period when monitor mode is enabled.
0A
(10)
Y 0–255 W
0XC1 (193) THERMAL INFORMATION
9:0
Temperature Output Status register to report the temperature of sensor. Updated
once per frame.
R
0XC2 (194) ANALOG CONTROLS
6
Reserved Reserved. 1 N 0, 1 W
MT9V032
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30
Table 8. REGISTER DESCRIPTIONS
0XC2 (194) ANALOG CONTROLS
7
Anti−Eclipse Enable Setting this bit turns on anti−eclipse circuitry. 0 N 0, 1 W
11:13 V_rst_lim voltage Level V_rst_lim = bits (2:0) × 50mV + 1.95V
Range: 1.95–2.30V; Default: 2.00V
Usage: For anti−eclipse reference voltage control
1 N 0–7 W
0XC3 (195) NTSC FRAME VALID CONTROL
0
Extend Frame Valid When set, frame valid is extended for half−line in length at
the odd field.
0 Y 0, 1 W
1 Replace FV/LV with
Ped/Snyc
When set, frame valid and line valid is replaced by ped and
sync signals respectively.
0 Y 0, 1 W
0XC4 (196) NTSC HORIZONTAL BLANKING CONTROL
7:0
Front porch width The front porch width in number of master clock cycle.
NTSC standard is 1.5msec ±0.1msec
16
(22)
Y 0–255 W
15:8 Sync Width The sync pulse width in number of master clock cycle.
NTSC standard is 4.7msec ±0.1msec.
044
(68)
Y 0–255 W
0XC5 (197) NTSC VERTICAL BLANKING CONTROL
7:0
Equalizing Pulse Width The pulse width in number of master clock cycle. NTSC
standard is 2.3msec ±0.1msec.
21
(33)
Y 0–255 W
15:8 Vertical Serration Width The pulse width in number of master clock cycle. NTSC
standard is 4.7msec ±0.1msec.
44
(68)
Y 0–255 W
0XF0 (240) BYTEWISE ADDRESS
Bytewise Address Special address to perform 8−bit READs and WRITEs to
the sensor. See the “Two−Wire Serial Interface Sam-
ple Read and Write Sequences” for further details on how to
use this functionality.
0XFE (254) REGISTER LOCK
15:0
Register Lock Code To lock all registers except R0xFE, program data with
0xDEAD; to unlock two−wire serial interface, program data
with 0xBEEF. When two−wire serial interface is locked, any
subsequent two−wire serial interface write to register other
than to two−wire serial interface Protect Enable Register is
ignored until two−wire serial interface is unlocked.
To lock Register 13 only, program data with 0xDEAF; to
unlock, program data with 0xBEEF. When Register 13 is
locked, any subsequent two−wire serial interface write to
this register only is ignored until register is unlocked.
BEEF
(48879)
N 48879,
57005,
57007
W
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MT9V032C12STMH-GEVB

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Optical Sensor Development Tools WVGA 1/3" GS CIS HB
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