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MT9V032C12STMH-GEVB

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P61
MT9V032
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37
PIXEL INTEGRATION CONTROL
Total Integration
R0x0B Total Shutter Width (In Terms of Number of
Rows)
This register (along with the window width and horizontal
blanking registers) controls the integration time for the
pixels.
The actual total integration time,
t
INT, is:
t
INT
+ (Number of rows of integration x row time) ) overhead
(eq. 1)
where:
• The number of rows integration is equal to the result of
automatic exposure control (AEC) which may vary
from frame to frame, or, if AEC is disabled, the value in
R0x0B
• Row time = (R0x04 + R0x05) master clock periods
• Overhead = (R0x04 + R0x05 – 255) master clock
periods
Typically, the value of R0x0B (total shutter width) is
limited to the number of rows per frame (which includes
vertical blanking rows), such that the frame rate is not
affected by the integration time. If R0x0B is increased
beyond the total number of rows per frame, it is required to
add additional blanking rows using R0x06 as needed. A
second constraint is that
t
INT must be adjusted to avoid
banding in the image from light flicker. Under 60Hz flicker,
this means frame time must be a multiple of 1/120 of a
second. Under 50Hz flicker, frame time must be a multiple
of 1/100 of a second.
Changes to Integration Time
With automatic exposure control disabled (R0xAF, bit 0
is cleared to LOW), and if the total integration time (R0x0B)
is changed through the two−wire serial interface while
FRAME_VALID is asserted for frame n, the first frame
output using the new integration time is frame (n + 2).
Similarly, when automatic exposure control is enabled, any
change to the integration time for frame n first appears in
frame (n + 2) output.
The sequence is as follows:
1. During frame n, the new integration time is held in
the R0x0B live register.
2. At the start of frame (n + 1), the new integration
time is transferred to the exposure control module.
Integration for each row of frame (n + 1) has been
completed using the old integration time. The
earliest time that a row can start integrating using
the new integration time is immediately after that
row has been read for frame (n + 1). The actual
time that rows start integrating using the new
integration time is dependent on the new value of
the integration time.
3. When frame (n + 1) is read out, it is integrated
using the new integration time. If the integration
time is changed (R0x0B written) on successive
frames, each value written is applied to a single
frame; the latency between writing a value and it
affecting the frame readout remains at two frames.
However, when automatic exposure control is
disabled, if the integration time is changed through
the two−wire serial interface after the falling edge
of FRAME_VALID for frame n, the first frame
output using the new integration time becomes
frame (n+3).
FRAME_VALID
LED_OUT
New Integration
Programmed
Actual
Integration
Image Data
Frame Start
Figure 20. Latency When Changing Integration
Int = 200 rows
Int = 300 rows
Int = 200 rows
Int = 300 rows
Output Image with
Int = 200 rows
Output
Image with
Int = 300 rows
MT9V032
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38
Exposure Indicator
The exposure indicator is controlled by:
• R0x1B LED_OUT control
The MT9V032 provides an output pin, LED_OUT, to
indicate when the exposure takes place. When R0x1B bit 0
is clear, LED_OUT is HIGH during exposure. By using
R0x1B, bit 1, the polarity of the LED_OUT pin can be
inverted.
High Dynamic Range
High dynamic range is controlled by:
• R0x08 shutter width 1
• R0x09 shutter width 2
• R0x0A shutter width control
• R0x31–R0x34 V_Step voltages
In the MT9V032, high dynamic range (that is, R0x0F, bit
6 = 1) is achieved by controlling the saturation level of the
pixel (HDR or high dynamic range gate) during the exposure
period. The sequence of the control voltages at the HDR gate
is shown in Figure 21. After the pixels are reset, the step
voltage, V_Step, which is applied to HDR gate, is set up at
V1 for integration time t
1
then to V2 for time t
2
, then V3 for
time t
3
, and finally it is parked at V4, which also serves as
an antiblooming voltage for the photodetector. This
sequence of voltages leads to a piecewise linear pixel
response, illustrated (in approximates) in Figure 21.
V
AA
(3.3V)
Figure 21. Sequence of Control Voltages at the HDR Gate
Exposure
HDR
Voltage
V1~1.4V
V2~1.2V
V3~1.0V
V4~0.8V
t
1
t
2
t
3
V
AA
(3.3V)
V1~1.4V
V2~1.2V
V3~1.0V
t
1
t
2
t
3
Output
Light Intensity
dV1
dV2
dV3
1/t
1
1/t
22
1/t
3
Figure 22. Sequence of Voltages in a Piecewise Linear Pixel Response
The parameters of the step voltage V_Step which takes
values V1, V2, and V3 directly affect the position of the knee
points in Figure 22.
Light intensities work approximately as a reciprocal of the
partial exposure time. Typically,
t
1 is the longest exposure,
t
2 shorter, and so on. Thus the range of light intensities is
shortest for the first slope, providing the highest sensitivity.
The register settings for V_Step and partial exposures are:
V1 = R0x31, bits 4:0
V2 = R0x32, bits 4:0
V3 = R0x33, bits 4:0
V4 = R0x34, bits 4:0
t
INT =
t
1 +
t
2 +
t
3
There are two ways to specify the knee points timing, the
first by manual setting (default) and the second by automatic
knee point adjustment.
When the auto adjust enabler is set to HIGH (LOW by
default), the MT9V032 calculates the knee points
automatically using the following equations:
t
1
+ t
INT
* t
2
* t
3
(eq. 2)
åt
2
+ t
INT
x(1ń2)
R0x0A,bits3:0
(eq. 3)
åt
3
+ t
INT
x(1ń2)
R0x0A,bits7:4
(eq. 4)
As a default for auto exposure,
t
2 is 1/16 of
t
INT,
t
3 is 1/64
of
t
INT.
MT9V032
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39
When the auto adjust enabler is disabled (default),
t
1,
t
2,
and
t
3 may be programmed through the two−wire serial
interface:
t
1
+ (R0x08, bits 14:0)
(eq. 5)
t
2
+ (R0x09, bits 14:0) * (R0x08,bits 14:0)
(eq. 6)
t
3
+ t
INT
* t
1
* t
2
(eq. 7)
t
INT may be based on the manual setting of R0x0B or the
result of the AEC. If the AEC is enabled then the auto knee
adjust must also be enabled.
Variable ADC Resolution
By default, ADC resolution of the sensor is 10−bit.
Additionally, a companding scheme of 12−bit into 10−bit is
enabled by the R0x1C (28). This mode allows higher ADC
resolution which means less quantization noise at low−light,
and lower resolution at high light, where good ADC
quantization is not so critical because of the high level of the
photon’s shot noise.
10−bit
Codes
1,024
768
512
256
256 512 1,024 2,048 4,096
12−bit
Codes
8 to 1 Companding (2,048 256)
4 to 1 Companding (1,536 384)
2 to 1 Companding (256 128)
No companding (256 256)
Figure 23. 12−to 10−Bit Companding Chart
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MT9V032C12STMH-GEVB

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Buy MT9V032C12STMH-GEVB
Manufacturer:
ON Semiconductor
Description:
Optical Sensor Development Tools WVGA 1/3" GS CIS HB
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