MT9V032
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This is to ensure the column pointer does not go beyond
the limit the MT9V032 can support.
Automatic Gain Control and Automatic Exposure
Control
The integrated AEC/AGC unit is responsible for ensuring
that optimal auto settings of exposure and (analog) gain are
computed and updated every frame.
Automatic exposure control (AEC) and automatic gain
control (AGC) can be individually enabled or disabled by
R0xAF. When AEC is disabled (R0xAF[0] = 0), the sensor
uses the manual exposure value in R0x0B. When AGC is
disabled (R0xAF[1] = 0), the sensor uses the manual gain
value in R0x35. See ON Semiconductor Technical Note
TN−09−81, “MT9V032 AEC and AGC Functions,” for
further details.
MAX. EXPOSURE
(R
0xBD)
DESIRED BIN
(desired luminance)
(R
0xA5)
MAX. GAIN
(R
0x36)
EXP. LPF
(R
0xA8)
EXP. SKIP
(R0xA6)
MANUAL EXP.
(R0x08)
AEC ENABLE
(R0Xaf[0])
To exposure
timing control
To analog
gain control
R
0xBA
AEC
OUTPUT
R
0xBB
AGC OUTPUT
MIN GAIN
MIN EXP
GAIN LPF
(R
0xAB)
GAIN SKIP
(R0xA9)
MANUAL GAIN
(R0x35)
AGC ENABLE
(R0xAF[1])
CURRENT BIN
(current luminance
(R0xBC)
AEC
UNIT
HISTOGRAM
GENERATOR
UNIT
AGC
UNIT
1
16
Figure 27. Controllable and Observable AEC/AGC Registers
0
1
1
0
The exposure is measured in row−time by reading
R0xBB. The exposure range is 1 to 2047. The gain is
measured in gain−units by reading R0xBA. The gain range
is 16 to 63 (unity gain = 16 gain−units; multiply by 1/16 to
get the true gain).
When AEC is enabled (R0xAF[0] = 1), the maximum auto
exposure value is limited by R0xBD; minimum auto
exposure is fixed at 1 row.
When AGC is enabled (R0xAF[1] = 1), the maximum
auto gain value is limited by R0x36; minimum auto gain is
fixed to 16 gain−units.
The exposure control measures current scene luminosity
and desired output luminosity by accumulating a histogram
of pixel values while reading out a frame. The desired
exposure and gain are then calculated from this for
subsequent frame.
Pixel Clock Speed
The pixel clock speed is same as the master clock
(SYSCLK) at 26.66 MHz by default. However, when
column binning 2 or 4 (R0x0D, bit 2 or 3) is enabled, the
pixel clock speed is reduced by half and one−fourth of the
master clock speed respectively. See “Read Mode Options”
and “Column Binning” for additional information.
Hard Reset of Logic
The RC circuit for the MT9V032 uses a 10kW resistor and
a 0.1mF capacitor. The rise time for the RC circuit is 1ms
maximum.
Soft Reset of Logic
Soft reset of logic is controlled by:
• R0x0C reset
Bit 0 is used to reset the digital logic of the sensor while
preserving the existing two−wire serial interface
configuration. Furthermore, by asserting the soft reset, the
sensor aborts the current frame it is processing and starts
a new frame. Bit 1 is a shadowed reset control register bit to
explicitly reset the automatic gain and exposure control
feature.
These two bits are self−resetting bits and also return to “0”
during two−wire serial interface reads.
STANDBY Control
The sensor goes into standby mode by setting STANDBY
to HIGH. Once the sensor detects that STANDBY is
asserted, it completes the current frame before disabling the
digital logic, internal clocks, and analog power enable
signal. To release the sensor from the standby mode, reset
