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SENSOR
SENSOR
26.6 MHz
Osc.
DS92LV16
LVDS
SER_DATAOUT
LVDS
SER_DATAIN
LVDS
BYPASS_CLKIN
LVDS
SHIFT_CLKOUT
5 meters (maximum)
PIXEL
FROM
MASTER
PIXEL
FROM
SLAVE
LV and FV are embedded in the data stream
82
Figure 47. Stereoscopic Topology
SLAVE
MASTER
LVDS
SER_DATAOUT
LVDS
SHIFT_CLKOUT
26.6 MHz
Osc.
LVDS
BYPASS_CLKIN
LVDS
SER_DATAIN
Typical configuration of the master and slave sensors:
1. Power up the sensors.
2. Broadcast WRITE to deassert LVDS
powerdown (set R0xB1[1] = 0).
3. Individual WRITE to master sensor putting its
internal PLL into bypass mode (set R0xB1[0] = 1).
4. Broadcast WRITE to both sensors to set the
stereoscopy bit (set R0x07[5] = 1).
5. Make sure all resolution, vertical blanking,
horizontal blanking, window size, and AEC/AGC
configurations are done through broadcast WRITE
to maintain lockstep.
6. Broadcast WRITE to enable LVDS driver (set
R0xB3[4] = 0).
7. Broadcast WRITE to enable LVDS receiver (set
R0xB2[4] = 0).
8. Individual WRITE to master sensor, putting its
internal PLL into bypass mode (set R0xB1[0] = 1).
9. Individual WRITE to slave sensor, enabling its
internal PLL (set R0xB1[0] = 0).
10. Individual WRITE to slave sensor, setting it as a
stereo slave (set R0x07[6] = 1).
11. Individual WRITEs to master sensor to minimize
the intersensor skew (set R0xB2[2:0],
R0xB3[2:0], and R0xB4[1:0] appropriately). Use
R0xB7 and R0xB8 to get lockstep feedback from
stereo_error_flag.
12. Broadcast WRITE to issue a soft reset (set
R0x0C[0] = 1 followed by R0x0C[0] = 0).
NOTE: The stereo_error_flag is set if a mismatch has
occurred at a reserved byte (slave and master
sensors codes at this reserved byte must match).
If the flag is set, steps 11 and 12 are repeated
until the stereo_error_flag remains cleared.
Broadcast and Individual Writes for Stereoscopic
Topology
In stereoscopic mode, the two sensors are required to run
in lockstep. This implies that control logic in each sensor is
in exactly the same state as its pair on every clock. To ensure
this, all inputs that affect control logic must be identical and
arrive at the same time at each sensor.
These inputs include:
system clock
system reset
twowire serial interface clk SCL
twowire serial interface data SDA
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SLAVE
SENSOR
MASTER
SENSOR
CLK
HOST
26.6 MHz
Osc.
CLKS_CTRL_ADR[0] CLKS_CTRL_ADR[0]
SDASCL SDASCL
SCL
SDA
L
L
L
Host launches SCL and SDA on positive
edge of SYSCLK
All system clock lengths (L) must be equal.
SCL and SDA lengths to each sensor (from the host) must also be equal.
Figure 48. TwoWire Serial Interface Configuration in Stereoscopic Mode
The setup in Figure 48 shows how the two sensors can
maintain lockstep when their configuration registers are
written through the twowire serial interface. A WRITE to
configuration registers would either be broadcast
(simultaneous WRITES to both sensors) or individual
(WRITE to just one sensor at a time). READs from
configuration registers would be individual (READs from
just one sensor at a time).
One of the two serial interface slave address bits of the
sensor is hardwired. The other is controlled by the host. This
allows the host to perform either a broadcast or a onetoone
access.
Broadcast WRITES are performed by setting the same
S_CTRL_ADR input bit for both slave and master sensor.
Individual WRITES are performed by setting opposite
S_CTRL_ADR input bit for both slave and master sensor.
Similarly, individual READs are performed by setting
opposite S_CTRL_ADR input bit for both slave and master
sensor.
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APPENDIX B POWERON RESET AND STANDBY TIMING
Reset, Clocks, and Standby
There are no constraints concerning the order in which the
various power supplies are applied; however, the MT9V032
requires reset in order operate properly at powerup. Refer
to Figure 49 for the powerup, reset, and standby sequences.
Figure 49. Powerup, Reset, Clock and Standby Sequence
nonLowPower
LowPower
nonLowPower
Power
down
Wake
up
ActiveStandby
PreStandbyActive
Power
up
MIN 20 SYSCLK cycles
Note 3
RESET #
STANDBY
SYSCLK
MIN 10 SYSCLK cycles
Does not
respond to
serial
interface
when
STANDBY = 1
MIN 10 SYSCLK cycles
MIN 10 SYSCLK cycles
D
OUT
[9:0]
D
OUT
[9:0]
DATA OUTPUT
SCLK, S
DATA
TwoWire
Serial
I/F
Driven
=
0
V
DD,
V
DD
LVDS
V
AA,
VAAPIX
1. All output signals are defined during initial powerup with RESET# held LOW without SYSCLK being active. To properly
reset the rest of the sensor, during initial powerup, assert RESET# (set to LOW state) for at least 750ns after all power
supplies have stabilized and SYSCLK is active (being clocked). Driving RESET# to LOW state does not put the part in
a low power state.
2. Before using twowire serial interface,wait for 10 SYSCLK rising edges after RESET# is deasserted.
3. Once the sensor detects that STANDBY has been asserted, it completes the current frame readout before entering
standby mode. The user must supply enough SYSCLKs to allow a complete frame raedout. See Table 4, “Frame Time,”
for more information.
4. In standby, all video data and synchronization output signals are HighZ.
5. In standby, the twowire serial interface is not active.
Standby Assertion Restrictions
STANDBY cannot be asserted at any time. If STANDBY
is asserted during a specific window within the vertical
blanking period, the MT9V032 may enter a permanent
standby state. This window (that is, dead zone) occurs prior
to the beginning of the new frame readout. The permanent
standby state is identified by the absence of the
FRAME_VALID signal on frame readouts. Issuing a
hardware reset (RESET# set to LOW state) will return the
image sensor to default startup conditions.
This dead zone can be avoided by:
1. Asserting STANDBY during the valid frame
readout time (FRAME_VALID is HIGH) and
maintaining STANDBY assertion for a minimum
of one frame period.
2. Asserting STANDBY at the end of valid frame
readout (falling edge of FRAME_VALID) and
maintaining STANDBY assertion for a minimum
of [5 + R0x06] rowtimes.
When STANDBY is asserted during the vertical blanking
period (FRAME_VALID is LOW), the STANDBY signal
must not change state between [Vertical Blanking Register
(R0x06) 5] rowtimes and [Vertical Blanking Register
+ 5] rowtimes after the falling edge of FRAME_VALID.

MT9V032C12STMH-GEVB

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Manufacturer:
ON Semiconductor
Description:
Optical Sensor Development Tools WVGA 1/3" GS CIS HB
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