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22
Table 8. REGISTER DESCRIPTIONS
0X09 (9) SHUTTER WIDTH 2
7:4
T3 Ratio Onehalf to the power of this value indicates the ratio of
duration time t
3
, when saturation control gate is adjusted to
level V3 to total integration when exposure knee point auto
adjust control bit is enabled. This register is not shadowed,
but any change made does not take effect until the following
new frame.
t
3
= Total integration × (½)
t3_ratio
.
Note: t
1
= Total integration t
2
t
3
.
6 N 0–15 W
8 Exposure Knee Point
Auto Adjust Enable
0 = Auto adjust disabled.
1 = Auto adjust enabled.
1 N 0,1 W
9 Single Knee Enable 0 = Single knee disabled.
1 = Single knee enabled.
0 N 0,1 W
0X0B (11) TOTAL SHUTTER WIDTH
14:0
Total Shutter Width Total integration time in number of rows. This value is used
only when AEC is disabled only (bit 0 of Register 175). This
register is not shadowed, but any change made does not
take effect until the following new frame.
1E0
(480)
N 1–32767 W
0X0C (12) RESET
0
Soft Reset Setting this bit causes the sensor to abandon the current
frame by resetting all digital logic except twowire serial
interface configuration. This is a selfresetting register bit
and should always read “0.” (This bit deasserts internal
active LOW reset signal for 15 clock cycles.)
0 N 0, 1 W
1 Auto Block Soft Reset Setting this bit causes the sensor to reset the automatic
gain and exposure control logic. This is a selfresetting
register bit and should always read “0.” (This bit deasserts
internal active LOW reset signal for 15 clock cycles.)
0 Y 0, 1 W
0X0D (13) READ MODE
1:0
Row Bin 0 = Normal operation.
1 = Row bin 2. Two pixel rows are read per row output.
Image size is effectively reduced by a factor of 2 vertically
while data rate and pixel clock are not affected. Resulting
frame rate is increased by 2.
2 = Row bin 4. Four pixel rows are read per row output.
Image size is effectively reduced by a factor of 4 vertically
while data rate and pixel clock are not affected. Resulting
frame rate is increased by 4.
3 = Not valid.
0 Y 0, 1, 2 W
3:2 Column Bin 0 = Normal operation.
1 = Column bin 2. When set, image size is reduced by a
factor of 2 horizontally. Frame rate is not affected but data
rate and pixel clock are reduced by onehalf that of
master clock.
2 = Column bin 4. When set, image size is reduced by a
factor of 4 horizontally. Frame rate is not affected but data
rate and pixel clock are reduced by onefourth that of
master clock.
3 = Not valid.
0 Y 0, 1, 2 W
4 Row Flip Read out rows from bottom to top (upside down). When set,
row readout starts from row (Row Start + Window Height)
and continues down to (Row Start + 1). When clear, readout
starts at Row Start and continues to (Row Start + Window
Height 1). This ensures that the starting color is main-
tained.
0 Y 0, 1 W
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23
Table 8. REGISTER DESCRIPTIONS
0X09 (9) SHUTTER WIDTH 2
5
Column Flip Read out columns from right to left (mirrored). When set,
column readout starts from column (Col Start + Window
Width) and continues down to (Col Start + 1). When clear,
readout starts at Col Start and continues to (Col Start +
Window Width 1). This ensures that the starting color is
maintained.
0 Y 0, 1 W
6 Show Dark Rows When set, the programmed dark rows is output before the
active window. Frame valid is thus asserted earlier than
normal. This has no effect on integration time or frame rate.
Whether the dark rows are shown in the image or not the
definition frame start is before the dark rows are read out.
0 Y 0, 1 W
7 Show Dark Columns When set, the programmed dark columns are output before
the active pixels in a line. Line valid is thus asserted earlier
than normal, and the horizontal blank time gets shorter by
18 pixel clocks.
0 Y 0, 1 W
9:8 Reserved Reserved. 3
0X0E (14) MONITOR MODE
0
Monitor Mode Enable Setting this bit puts the sensor into a cycle of sleeping for
five minutes, and waking up to capture a programmable
number of frames (R0xC0). Clearing this bit resumes nor-
mal operation.
0 Y 0, 1 W
0X0F (15) PIXEL OPERATION MODE
2
Color/Mono Should be set according to sensor type:
0 = Monochrome.
1 = Color.
0 Y 0, 1 W
6 High Dynamic Range 0 = Linear operation.
1 = High Dynamic Range. Voltage and shutter width must
be correctly set for saturation control to operate.
0 Y 0, 1 W
0X1B (27) LED_OUT CONTROL
0
Disable LED_OUT Disable LED_OUT output. When cleared, the output pin
LED_OUT is pulsed high when the sensor is undergoing
exposure.
0 Y 0, 1 W
1 Invert LED_OUT Invert polarity of LED_OUT output. When set, the output pin
LED_OUT is pulsed low when the sensor is undergoing
exposure.
0 Y 0, 1 W
0X1C (28) ADC RESOLUTION CONTROL
1:0
ADC Mode 0 = Invalid.
1 = Invalid.
2 = 10bit linear.
3 = 12to10bit companding.
2 Y 2, 3 W
0X2C (44) VREF_ADC CONTROL
2:0
VREF_ADC Voltage
Level
0 = VREF_ADC = 1.0V.
1 = V
REF_ADC = 1.1V.
2 = VREF_ADC = 1.2V.
3 = VREF_ADC = 1.3V.
4 = V
REF_ADC = 1.4V.
5 = VREF_ADC = 1.5V.
6 = V
REF_ADC = 1.6V.
7 = VREF_ADC = 2.1V.
Range: 1.0–2.1V; Default: 1.4V
V
REF_ADC for ADC.
4 N 0–7 W
0X31 (49) V1 CONTROL
4:0
V1 voltage level V_Step = bits (4:0) x 62.5mV + 0.5625V.
Range: 0.5625 2.5V; Default: 2.375V.
Usage: V_Step1 HiDy voltage.
1D
(29)
N 0–31 W
0X32 (50) V2 CONTROL
MT9V032
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24
Table 8. REGISTER DESCRIPTIONS
0X32 (50) V2 CONTROL
4:0
V2 voltage level V_Step = bits (4:0) x 62.5mV + 0.5625V.
Range: 0.5625 2.5V; Default: 2.0625V.
Usage: V_Step2 HiDy voltage.
18
(24)
N 0–31 W
0X33 (51) V3 CONTROL
4:0
V3 voltage level V_Step = bits (4:0) x 62.5mV + 0.5625V.
Range: 0.5625 2.5V; Default: 1.875V.
Usage: V_Step3 HiDy voltage.
15
(21)
N 0–31 W
0X34 (52) V4 CONTROL
4:0
V4 voltage level V_Step = bits (4:0) x 62.5mV + 0.5625V.
Range: 0.5625 2.5V; Default: 0.8125V.
Usage: V_Step HiDy parking voltage, also provides anti
blooming when V_Step is disabled.
4 N 0–31 W
0X35 (53) ANALOG GAIN
6:0
Analog Gain Analog gain = bits (6:0) x 0.0625 for values 16–31
Analog gain = bits (6:0)/2 x 0.125 for values 32–64
For values 16–31: each LSB increases analog gain
0.0625v/v. A value of 16 = 1X gain. Range: 1X to 1.9375X
For values 32–64: each 2 LSB increases analog gain
0.125v/v. Range: 2X to 4X. An LSB increase of 1 will not
increase the gain; the value must be incremented by 2
No exception detection is installed and caution
should be taken when programming
10
(16)
Y 16–64 W
0X36 (54) MAXIMUM ANALOG GAIN
6:0
Maximum Analog Gain This register is used by the automatic gain control (AGC) as
the upper threshold of gain. This ensures the new calibrated
gain value does not exceed that which the MT9V032 sup-
ports.
Range: 16
dec
–64
dec
for 1X–4X respectively. Note: No ex-
ception detection is installed; caution should be taken when
programming.
40
(64)
Y 16–64 W
0X42 (66) FRAME DARK AVERAGE
7:0
Frame Dark Average The value read is the frame averaged black level, that is,
used in the black level algorithm calculations.
0 R
0X46 (70) DARK AVERAGE THRESHOLDS
7:0
Lower threshold Lower threshold for targeted black level in ADC LSBs. 1D
(29)
N 0–255 W
15:8 Upper threshold Upper threshold for targeted black level in ADC LSBs. 23
(35)
N 0–255 W
0X47 (71) BLACK LEVEL CALIBRATION CONTROL
0
Manual Override Manual override of black level correction.
1 = Override automatic black level correction with pro-
grammed values. (R0x48).
0 = Normal operation (default).
0 N 0, 1 W
7:5 Frames to average over Two to the power of this value decide how many frames to
average over when the black level algorithm is in the aver-
aging mode. In this mode the running frame average is
calculated from the following formula:
Running frame ave = Old running frame ave (old running
frame ave)/2n + (new frame ave)/ 2n.
4 N 0–7 W
15:8 Reserved Reserved. 80
(128)
0X48 (72) BLACK LEVEL CALIBRATION VALUE

MT9V032C12STMH-GEVB

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Optical Sensor Development Tools WVGA 1/3" GS CIS HB
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