MT9V032
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57
APPENDIX A − SERIAL CONFIGURATIONS
With the LVDS serial video output, the deserializer can be
up to 8 meters from the sensor. The serial link can save on
the cabling cost of 14 wires (D
OUT[9:0], LINE_VALID,
FRAME_VALID, PIXCLK, GND). Instead, just three wires
(two serial LVDS, one GND) are sufficient to carry the video
signal.
Configuration of Sensor for Stand − Alone Serial
Output with Internal PLL
In this configuration, the internal PLL generates the
shift−clk (x12). The LVDS pins SER_DATAOUT_P and
SER_DATAOUT_N must be connected to a deserializer
(clocked at approximately the same system clock
frequency).
Figure 46 shows how a standard off−the−shelf deserializer
(National Semiconductor DS92LV1212A) can be used to
retrieve the standard parallel video signals of D
OUT(9:0),
LINE_VALID and FRAME_VALID.
Sensor
CLK
26.6 Mhz
Osc.
26.6 Mhz
Osc.
DS92LV1212A
LVDS
SER_DATAOUT
LVDS
SER_DATAIN
LVDS
BYPASS_CLKIN
LVDS
SHIFT_CLKOUT
8 meters (maximum)
LINE_VALID
FRAME_VALID
PIXEL
8−bit configuration shown
82
Figure 46. Stand−Alone Topology
Typical configuration of the sensor:
1. Power up sensor.
2. Enable LVDS driver (set R0xB3[4]= 0).
3. De−assert LVDS power−down (set R0xB1[1] = 0.
4. Issue a soft reset (set R0x0C[0] = 1 followed by
R0x0C[0] = 0.
If necessary:
5. Force sync patterns for the deserializer to lock (set
R0xB5[0] = 1).
6. Stop applying sync patterns (set R0xB5[0] = 0).
Configuration of Sensor for
Stereoscopic Serial Output with Internal
PPL
In this configuration the internal PLL generates the
shift−clk (x18) in phase with the system−clock. The LVDS
pins SER_DATAOUT_P and SER_DATAOUT_N must be
connected to a deserializer (clocked at approximately the
same system clock frequency).
Figure 47 shows how a standard off−the−shelf deserializer
can be used to retrieve back D
OUT(9:2) for both the master
and slave sensors. Additional logic is required to extract out
LINE_VALID and FRAME_VALID embedded within the
pixel data stream.
