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UJA1069TW/5V0/C/T,

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P64
UJA1069_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 28 October 2009 13 of 64
NXP Semiconductors
UJA1069
LIN fail-safe system basis chip
6.4.1 Watchdog start-up behavior
Following any reset event the watchdog is used to monitor the ECU start-up procedure. It
observes the behavior of the RSTN pin for any clamping condition or interrupted reset
wire. In case the watchdog is not properly served within t
WD(init)
, another reset is forced
and the monitoring procedure is restarted. In case the watchdog is again not properly
served, the system enters Fail-safe mode (see also Figure 4, Start-up mode and Restart
mode).
6.4.2 Watchdog window behavior
Whenever the SBC enters Normal mode, the Window mode of the watchdog is activated.
This ensures that the microcontroller operates within the required speed; a too fast as well
as a too slow operation will be detected. Watchdog triggering using the Window mode is
illustrated in Figure 5.
The SBC provides 10 different period timings, scalable with a 4-factor watchdog prescaler.
The period can be changed within any valid trigger window. Whenever the watchdog is
triggered within the window time, the timer will be reset to start a new period.
The watchdog window is defined to be between 50 % and 100 % of the nominal
programmed watchdog period. Any too early or too late watchdog access or wrong Mode
register code access will result in an immediate system reset, entering Start-up mode.
Fig 5. Watchdog triggering using Window mode
mce626
trigger window
trigger
window
too early
trigger
restarts
period
50 %
trigger
via SPI
trigger
via SPI
last
trigger point
earliest possible
trigger point
latest possible
trigger point
earliest
possible
trigger
point
latest
possible
trigger
point
too early
trigger restarts period
(with different duration if
desired)
period
100 %
50 % 100 %
new period
UJA1069_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 28 October 2009 14 of 64
NXP Semiconductors
UJA1069
LIN fail-safe system basis chip
6.4.3 Watchdog time-out behavior
Whenever the SBC operates in Standby mode, in Sleep mode or in Flash mode, the active
watchdog operates in Time-out mode. The watchdog has to be triggered within the actual
programmed period time; see Figure 6. The Time-out mode can be used to provide cyclic
wake-up events to the host microcontroller from Standby mode and Sleep mode.
In Standby and in Flash mode the nominal periods can be changed with any SPI access
to the Mode register.
Any illegal watchdog trigger code results in an immediate system reset, entering Start-up
mode.
6.4.4 Watchdog OFF behavior
In Standby mode and Sleep mode it is possible to switch off the watchdog entirely. For
fail-safe reasons this is only possible if the microcontroller has stopped program
execution. To ensure that there is no program execution, the V1 supply current is
monitored by the SBC while the watchdog is switched off.
When selecting the watchdog OFF code, the watchdog remains active until the
microcontroller supply current has dropped below the current monitoring threshold I
thL(V1)
.
After the supply current has dropped below the threshold, the watchdog stops at the end
of the watchdog period. In case the supply current does not drop below the monitoring
threshold, the watchdog stays active.
If the microcontroller supply current increases above I
thH(V1)
while the watchdog is OFF,
the watchdog is restarted with the last used watchdog period time and a watchdog restart
interrupt is forced, if enabled.
In case of a direct mode change towards Standby mode with watchdog OFF selected, the
longest possible watchdog period is used. It should be noted that in Sleep mode V1
current monitoring is not active.
Fig 6. Watchdog triggering using Time-out mode
mce627
trigger
via SPI
earliest
possible
trigger
point
latest
possible
trigger
point
trigger restarts period
(with different duration if
desired)
new period
trigger range
trigger range time-out
time-out
period
UJA1069_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 28 October 2009 15 of 64
NXP Semiconductors
UJA1069
LIN fail-safe system basis chip
6.5 System reset
The reset function of the UJA1069 offers two signals to deal with reset events:
• RSTN; the global ECU system reset
• EN; a fail-safe global enable signal
6.5.1 RSTN pin
The system reset pin (RSTN) is a bidirectional input / output. Pin RSTN is active LOW with
selectable pulse length upon the following events; see Figure 4:
• Power-on (first battery connection) or V
BAT42
below power-on reset threshold voltage
• Low V1 supply
• V1 current above threshold during Standby mode while watchdog OFF behavior is
selected
• V3 is down due to short-circuit condition during Sleep mode
• RSTN externally forced LOW, falling edge event
• Successful preparation for Flash mode completed
• Successful exit from Flash mode
• Wake-up from Standby mode via pins LIN or WAKE if programmed accordingly, or any
wake-up event from Sleep mode
• Wake-up event from Fail-safe mode
• Watchdog trigger failures (too early, overflow, wrong code)
• Illegal mode code via SPI applied
• Interrupt not served within t
RSTN(INT)
All of these reset events have a dedicated reset source in the System Status register to
allow distinction between the different events.
The SBC will lengthen any reset event to 1 ms or 20 ms to ensure that external hardware
is properly reset. After the first battery connection, a short power-on reset of 1 ms is
provided after voltage V1 is present. Once started, the microcontroller can set the Reset
Length Control (RLC) bit within the System Configuration Register; this allows the reset
pulse to be adjusted for future reset events. With this bit set, all reset events are
lengthened to 20 ms. Due to fail-safe behavior, this bit will be set automatically (to 20 ms)
in Restart mode or Fail-safe mode. With this mechanism it is guaranteed that an
erroneously shortened reset pulse will restart any microcontroller, at least within the
second trial by using the long reset pulse.
The behavior of pin RSTN is illustrated in Figure 7. The duration of t
RSTNL
depends on the
setting of the RLC bit (defines the reset length). Once an external reset event is detected
the system controller enters the Start-up mode. The watchdog now starts to monitor pin
RSTN as illustrated in Figure 8. If the RSTN pin is not released in time then Fail-safe
mode is entered as shown in Figure 4.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P64

UJA1069TW/5V0/C/T,

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Buy UJA1069TW/5V0/C/T,
Manufacturer:
NXP Semiconductors
Description:
LIN Transceivers IC LIN FAIL-SAFE
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