UJA1069_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 28 October 2009 16 of 64
NXP Semiconductors
UJA1069
LIN fail-safe system basis chip
Pin RSTN is monitored for a continuously clamped LOW situation. Once the SBC pulls pin
RSTN HIGH but pin RSTN level remains LOW for longer than t
RSTN(CLT)
, the SBC
immediately enters Fail-safe mode since this indicates an application failure.
Fig 7. Reset pin behavior
Fig 8. Reset timing diagram
V
RSTN
power-up power-
down
under-
voltage
missing
watchdog
access
under-
voltage
spike
V1
time
time
V
rel(UV)(V1)
V
det(UV)(V1)
coa054
t
RSTNL
t
RSTNL
t
RSTNL
001aad181
RSTN
externally
forced LOW
RSTN externally forced LOW
time
time
V
RSTN
V
RSTN
t
RSTNL
t
WD(init)
t
RSTNL
t
WD(init)
UJA1069_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 28 October 2009 17 of 64
NXP Semiconductors
UJA1069
LIN fail-safe system basis chip
The SBC also detects if pin RSTN is clamped HIGH. If the HIGH-level remains on the pin
for longer than t
RSTN(CHT)
while pin RSTN is driven internally to a LOW-level by the SBC,
the SBC falls back immediately to Fail-safe mode since the microcontroller cannot be
reset any more. By entering Fail-safe mode, the V1 voltage regulator shuts down and the
microcontroller stops.
Additionally, chattering reset signals are handled by the SBC in such a way that the
system safely falls back to Fail-safe mode with the lowest possible power consumption.
6.5.2 EN output
Pin EN can be used to control external hardware such as power components or as a
general purpose output if the system is running properly. During all reset events, when pin
RSTN is pulled LOW, the EN control bit will be cleared, pin EN will be pulled LOW and will
stay LOW after pin RSTN is released. In Normal mode and Flash mode of the SBC, the
microcontroller can set the EN control bit via the SPI. This results in releasing pin EN
which then returns to a HIGH-level.
6.6 Power supplies
6.6.1 BAT14, BAT42 and SYSINH
The SBC has two supply pins, pin BAT42 and pin BAT14. Pin BAT42 supplies most of the
SBC where pin BAT14 only supplies the linear voltage regulators and the INH/LIMP output
pin. This supply architecture allows different supply strategies including the use of
external DC-to-DC converters controlled by the pin SYSINH.
6.6.1.1 SYSINH output
The SYSINH output is a high-side switch from BAT42. It is activated whenever the SBC
requires supply voltage to pin BAT14, e.g. when V1 is on (see Figure 4 and Figure 8).
Otherwise pin SYSINH is floating. Pin SYSINH can be used to control e.g. an external
step-down voltage regulator to BAT14, to reduce power consumption in low-power modes.
6.6.2 SENSE input
The SBC has a dedicated SENSE pin for dynamic monitoring of the battery contact of an
electronic control unit. Connecting this pin in front of the polarity protection diode of the
ECU provides an early warning if the battery becomes disconnected.
6.6.3 Voltage regulator V1
The UJA1069 has an independent voltage regulator supplied out of the BAT14 pin.
Regulator V1 is intended to supply the microcontroller.
The V1 voltage is continuously monitored to provide the system reset signal when
undervoltage situations occur. Whenever the V1 voltage falls below one of the three
programmable thresholds, a hardware reset is forced.
A dedicated V1 supply comparator (V1 Monitor) observes V1 for undervoltage events
lower than V
UV(VFI)
. This allows the application to receive a supply warning interrupt in
case one of the lower V1 undervoltage reset thresholds is selected.
The V1 regulator is overload protected. The maximum output current available from pin V1
depends on the voltage applied to pin BAT14 according to Table 25. For thermal reasons,
the total power dissipation should be taken into account.
UJA1069_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 28 October 2009 18 of 64
NXP Semiconductors
UJA1069
LIN fail-safe system basis chip
6.6.4 Switched battery output V3
V3 is a high-side switched BAT42-related output which is used to drive external loads
such as wake-up switches or relays. The features of V3 are as follows:
Three application controlled modes of operation; ON, OFF or Cyclic mode.
Two different cyclic modes allow the supply of external wake-up switches; these
switches are powered intermittently, thus reducing the system’s power consumption in
case a switch is continuously active; the wake-up input of the SBC is synchronized
with the V3 cycle time.
The switch is protected against current overloads. If V3 is overloaded, pin V3 is
automatically disabled. The corresponding Diagnosis register bit is reset and an
interrupt is forced (if enabled). During Sleep mode, a wake-up is forced and the
corresponding reset source code becomes available in the RSS bits of the System
Status register. This signals that the wake-up source via V3 supplied wake-up
switches has been lost.
6.7 LIN transceiver
The integrated LIN transceiver of the UJA1069 is a LIN 2.0 compliant transceiver. The
transceiver has the following features:
SAE J2602 compliant and compatible with LIN revision 1.3
Fail-safe LIN termination to BAT42 via dedicated RTLIN pin
Enhanced error handling and reporting of bus and TXD failures; these failures are
separately identified in the System Diagnosis register
6.7.1 Mode control
The controller of the LIN transceiver provides two modes of operation: Active mode and
Off-line mode; see Figure 9. In Off-line mode the transmitter and receiver do not consume
current, but wake-up events will be recognized by the separate wake-up receiver.

UJA1069TW/5V0/C/T,

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
LIN Transceivers IC LIN FAIL-SAFE
Lifecycle:
New from this manufacturer.
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