UJA1069_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 28 October 2009 43 of 64
NXP Semiconductors
UJA1069
LIN fail-safe system basis chip
Battery supply monitor input; pin SENSE
V
th(SENSE)
input threshold low
battery voltage
detection 1 2.5 3 V
release 1.7 - 4 V
I
IH(SENSE)
HIGH-level input
current
Normal mode; BATFIE = 1 20 50 100 µA
Standby mode; BATFIE = 1 5 10 20 µA
Normal mode or Standby
mode; BATFIE = 0
- 0.2 2 µA
Voltage source; pin V1; see also
Figure 17 to Figure 23
V
o(V1)
output voltage V
BAT14
= 5.5 V to 18 V;
I
V1
= 120 mA to 5 mA;
T
j
=25°C
V
V1(nom)
0.1
V
V1(nom)
V
V1(nom)
+
0.1
V
V
BAT14
= 14 V; I
V1
= 5 mA;
T
j
=25°C
V
V1(nom)
0.025
V
V1(nom)
V
V1(nom)
+
0.025
V
V
V1
supply voltage
regulation
V
BAT14
= 9 V to 16 V;
I
V1
= 5 mA; T
j
=25°C
- 1 25 mV
load regulation V
BAT14
=14V;
I
V1
= 50 mA to 5 mA;
T
j
=25°C
- 5 25 mV
voltage drift with
temperature
V
BAT14
= 14 V; I
V1
= 5 mA;
T
j
= 40 °C to +150 °C
[2]
- - 200 ppm/K
V
det(UV)(V1)
undervoltage
detection and reset
activation level
V
BAT14
=14V;
V1RTHC[1:0] = 00 or 11
0.90 ×
V
V1(nom)
0.92 ×
V
V1(nom)
0.95 ×
V
V1(nom)
V
V
BAT14
=14V;
V1RTHC[1:0] = 01
0.80 ×
V
V1(nom)
0.82 ×
V
V1(nom)
0.85 ×
V
V1(nom)
V
V
BAT14
=14V;
V1RTHC[1:0] = 10
0.70 ×
V
V1(nom)
0.72 ×
V
V1(nom)
0.75 ×
V
V1(nom)
V
V
rel(UV)(V1)
undervoltage
detection release
level
V
BAT14
= 14 V;
V1RTHC[1:0] = 00 or 11
- 0.94 ×
V
V1(nom)
-V
V
BAT14
= 14 V;
V1RTHC[1:0] = 01
- 0.84 ×
V
V1(nom)
-V
V
BAT14
= 14 V;
V1RTHC[1:0] = 10
- 0.74 ×
V
V1(nom)
-V
V
UV(VFI)
undervoltage level
for generating a VFI
interrupt
V
BAT14
= 14 V; VFIE = 1 0.90 ×
V
V1(nom)
0.93 ×
V
V1(nom)
0.97 ×
V
V1(nom)
V
I
thH(V1)
undercurrent
threshold for
watchdog enable
10 5 2mA
I
thL(V1)
undercurrent
threshold for
watchdog disable
6 3 1.5 mA
Table 25. Static characteristics
…continued
T
vj
=
40
°
C to +150
°
C, V
BAT42
=5.5Vto52V;V
BAT14
=5.5Vto27V;V
BAT42
V
BAT14
1 V; unless otherwise specified. All
voltages are defined with respect to ground. Positive currents flow into the IC.
[1]
Symbol Parameter Conditions Min Typ Max Unit
UJA1069_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 28 October 2009 44 of 64
NXP Semiconductors
UJA1069
LIN fail-safe system basis chip
I
V1
output current
capability
V
BAT14
= 9 V to 27 V;
δV
V1
= 0.05 × V
V1(nom)
200 135 120 mA
V
BAT14
= 9 V to 27 V;
V1 shorted to GND
200 110 - mA
V
BAT14
=8V to9V;
δV
V1
= 0.05 × V
V1(nom)
--−120 mA
V
BAT14
= 5.5 V to 8 V;
δV
V1
= 0.05 × V
V1(nom)
--150 mA
Z
ds(on)
regulator impedance
between pins BAT14
and V1
V
BAT14
= 4 V to 5 V - 3 5
Voltage source; pin V3
V
BAT42-V3(drop)
V
BAT42
to V
V3
voltage
drop
V
BAT42
= 9 V to 52 V;
I
V3
= 20 mA
- - 1.0 V
I
det(OL)(V3)
overload current
detection threshold
V
BAT42
= 9 V to 52 V 165 - 60 mA
I
L
leakage current V
V3
= 0 V; V3C[1:0] = 00 - 0 5 µA
System inhibit output; pin SYSINH
V
BAT42-SYSINH(drop)
V
BAT42
to V
SYSINH
voltage drop
I
SYSINH
= 0.2 mA - 1.0 2.0 V
I
L
leakage current V
SYSINH
=0V - - 5 µA
Inhibit/limp-home output; pin INH/LIMP
V
BAT14-INH(drop)
V
BAT14
to V
INH
voltage drop
I
INH/LIMP
= 10 µA;
ILEN = ILC = 1
- 0.7 1.0 V
I
INH/LIMP
= 200 µA;
ILEN = ILC = 1
- 1.2 2.0 V
I
o(INH/LIMP)
output current
capability
V
INH/LIMP
= 0.4 V;
ILEN = 1; ILC = 0
0.8 - 4 mA
I
L
leakage current V
INH/LIMP
= 0 V to V
BAT14
;
ILEN = 0
--5µA
Wake input; pin WAKE
V
th(WAKE)
wake-up voltage
threshold
2.0 3.3 5.2 V
I
WAKE(pu)
pull-up input current V
WAKE
=0V 25 - 1.3 µA
Serial peripheral interface inputs; pins SDI, SCK and SCS
V
IH(th)
HIGH-level input
threshold voltage
0.7 × V
V1
-V
V1
+ 0.3 V
V
IL(th)
LOW-level input
threshold voltage
0.3 - +0.3 × V
V1
V
R
pd(SCK)
pull-down resistor at
pin SCK
V
SCK
=2V; V
V1
2 V 50 130 400 k
R
pu(SCS)
pull-up resistor at
pin SCS
V
SCS
=1V; V
V1
2 V 50 130 400 k
Table 25. Static characteristics
…continued
T
vj
=
40
°
C to +150
°
C, V
BAT42
=5.5Vto52V;V
BAT14
=5.5Vto27V;V
BAT42
V
BAT14
1 V; unless otherwise specified. All
voltages are defined with respect to ground. Positive currents flow into the IC.
[1]
Symbol Parameter Conditions Min Typ Max Unit
UJA1069_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 28 October 2009 45 of 64
NXP Semiconductors
UJA1069
LIN fail-safe system basis chip
I
SDI
input leakage current
at pin SDI
V
SDI
= 0 V to V
V1
5- +5µA
Serial peripheral interface data output; pin SDO
I
OH
HIGH-level output
current
V
SCS
=0V; V
O
=V
V1
0.4 V 50 - 1.6 mA
I
OL
LOW-level output
current
V
SCS
=0V; V
O
= 0.4 V 1.6 - 20 mA
I
OL(off)
OFF-state output
leakage current
V
SCS
=V
V1
; V
O
= 0 V to V
V1
5- +5µA
Reset output with clamping detection; pin RSTN
I
OH
HIGH-level output
current
V
RSTN
= 0.7 × V
V1(nom)
1000 - 50 µA
I
OL
LOW-level output
current
V
RSTN
= 0.9 V 1 - 5 mA
V
OL
LOW-level output
voltage
V
V1
= 1.5 V to 5.5 V;
pull-up resistor to V1 4 k
0 - 0.2 × V
V1
V
V
IH(th)
HIGH-level input
threshold voltage
0.7 × V
V1
-V
V1
+ 0.3 V
V
IL(th)
LOW-level input
threshold voltage
0.3 - +0.3 × V
V1
V
Enable output; pin EN
I
OH
HIGH-level output
current
V
OH
=V
V1
0.4 V 20 - 1.6 mA
I
OL
LOW-level output
current
V
OL
= 0.4 V 1.6 - 20 mA
V
OL
LOW-level output
voltage
I
OL
=20µA; V
V1
= 1.2 V 0 - 0.4 V
Interrupt output; pin INTN
I
OL
LOW-level output
current
V
OL
= 0.4 V 1.6 - 15 mA
LIN transmit data input; pin TXDL
V
IL
LOW level input
voltage
0.3 - +0.3 × V
V1
V
V
IH
HIGH-level input
voltage
0.7 × V
V1
-V
V1
+ 0.3 V
R
TXDL(pu)
TXDL pull-up
resistor
V
TXDL
= 0 V 5 12 25 k
LIN receive data output; pin RXDL
I
OH
HIGH-level output
current
V
RXDL
=V
V1
0.4 V 50 - 1.6 mA
I
OL
LOW-level output
current
V
RXDL
= 0.4 V 1.6 - 20 mA
Table 25. Static characteristics
…continued
T
vj
=
40
°
C to +150
°
C, V
BAT42
=5.5Vto52V;V
BAT14
=5.5Vto27V;V
BAT42
V
BAT14
1 V; unless otherwise specified. All
voltages are defined with respect to ground. Positive currents flow into the IC.
[1]
Symbol Parameter Conditions Min Typ Max Unit

UJA1069TW/5V0/C/T,

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
LIN Transceivers IC LIN FAIL-SAFE
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union