UJA1069_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 28 October 2009 56 of 64
NXP Semiconductors
UJA1069
LIN fail-safe system basis chip
[1] All parameters are guaranteed over the virtual junction temperature range by design. Products are 100 % tested at 125 °C ambient
temperature on wafer level (pretesting). Cased products are 100 % tested at 25 °C ambient temperature (final testing). Both pretesting
and final testing use correlated test conditions to cover the specified temperature and power supply voltage range.
[2] SPI timing is guaranteed for V
BAT42
voltages down to 5 V. For V
BAT42
voltages down to 4.5 V the guaranteed SPI timing values double, so
at these lower voltages a lower maximum SPI communication speed must be observed.
[3] t
bit
= selected bit time, depends on LSC bit; 50 µs or 96 µs (20 kbit/s or 10.4 kbit/s respectively); bus load conditions (R
1
/R
2
/C
1
):
1kΩ/1 kΩ/10 nF; 1 kΩ/2 kΩ/6.8 nF; 1 kΩ/open/1 nF; see Figure 25 and Figure 26.
[4]
[5]
Interrupt output; pin INTN
t
INTN
interrupt release after SPI has read out the
Interrupt register
2-- µs
Oscillator
f
osc
oscillator frequency 460.8 512 563.2 kHz
Table 26. Dynamic characteristics
…continued
T
vj
=
−
40
°
C to +150
°
C; V
BAT42
=5.5Vto52V;V
BAT14
=5.5Vto27V;V
BAT42
≥
V
BAT14
−
1 V; unless otherwise specified. All
voltages are defined with respect to ground. Positive currents flow into the IC.
[1]
Symbol Parameter Conditions Min Typ Max Unit
δ1 δ3,
t
bus rec()min()
2t
bit
×
-------------------------------
=
δ2 δ4,
t
bus rec()max()
2t
bit
×
--------------------------------
=
Fig 24. SPI timing
001aaa405
SCS
SCK
SDI
SDO X
X X
MSB LSB
MSB LSB
t
DOV
floating floating
t
h
t
su
t
SCKL
t
SCKH
t
lead
T
cyc
t
lag
t
SSH
