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UJA1069TW/5V0/C/T,

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P64
UJA1069_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 28 October 2009 58 of 64
NXP Semiconductors
UJA1069
LIN fail-safe system basis chip
12. Package outline
Fig 27. Package outline SOT549-1 (HTSSOP32)
UNIT A
1
A
2
A
3
b
p
cD
(1)
E
(2)
eH
E
LL
p
Zywv θ
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
mm
0.15
0.05
8
0
o
o
0.1
DIMENSIONS (mm are the original dimensions).
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
SOT549-1
03-04-07
05-11-02
w M
θ
A
A
1
A
2
E
h
D
h
D
L
p
detail X
E
Z
exposed die pad side
e
c
L
X
(A
3
)
0.25
1
16
32
17
y
b
H
E
0.95
0.85
0.30
0.19
D
h
5.1
4.9
E
h
3.6
3.4
0.20
0.09
11.1
10.9
6.2
6.0
8.3
7.9
0.65 1 0.2
0.78
0.48
0.1
0.75
0.50
p
v M
A
A
HTSSOP32: plastic thermal enhanced thin shrink small outline package; 32 leads;
body width 6.1 mm; lead pitch 0.65 mm; exposed die pad
SOT549-1
A
max.
1.1
0
2.5
5 mm
scale
pin 1 index
MO-153
UJA1069_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 28 October 2009 59 of 64
NXP Semiconductors
UJA1069
LIN fail-safe system basis chip
Fig 28. Package outline SOT864-1 (HTSSOP24)
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
SOT864-1
MO-153
SOT864-1
04-09-23
05-12-06
DIMENSIONS (mm are the original dimensions)
HTSSOP24: plastic thermal enhanced thin shrink small outline package; 24 leads;
body width 4.4 mm; lead pitch 0.65 mm; exposed die pad
θ
A
L
p
detail X
L
(A
3
)
A
2
A
1
b
p
A
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
D
Z
E
c
D
H
H
E
E
h
y
e
w
M
pin 1 index
exposed die pad
vA
M
X
0 2.5 5 mm
scale
UNIT
A
max
mm 1.1
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
7.9
7.7
4.5
4.3
6.6
6.2
0.75
0.50
0.5
0.2
A
1
A
2
A
3
0.25
b
p
c D
(1)
E
(2)
e
0.65
H
E
3.3
3.1
E
h
4.3
4.1
D
h
L
1
L
p
v
0.2
w
0.13
y
0.1
Z θ
8
°
0
°
112
24
13
UJA1069_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 28 October 2009 60 of 64
NXP Semiconductors
UJA1069
LIN fail-safe system basis chip
13. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note
AN10365 “Surface mount reflow
soldering description”
.
13.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
13.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
13.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P64

UJA1069TW/5V0/C/T,

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Buy UJA1069TW/5V0/C/T,
Manufacturer:
NXP Semiconductors
Description:
LIN Transceivers IC LIN FAIL-SAFE
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New from this manufacturer.
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