UJA1069_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 28 October 2009 25 of 64
NXP Semiconductors
UJA1069
LIN fail-safe system basis chip
6.12.1 SPI register mapping
Any control bit which can be set by software is readable by the application. This allows
software debugging as well as control algorithms to be implemented.
Watchdog serving and mode setting is performed within the same access cycle; this only
allows an SBC mode change whilst serving the watchdog.
Each register carries 12 data bits; the other 4 bits are used for register selection and
read/write definition.
6.12.2 Register overview
The SPI interface gives access to all SBC registers; see Table 3. The first two bits (A1 and
A0) of the message header define the register address, the third bit is the Read Register
Select bit (RRS) to select one out of two possible feedback registers; the fourth bit (RO)
allows ‘read only’ access to one of the feedback registers. Which of the SBC registers can
be accessed also depends on the SBC operating mode.
6.12.3 Mode register
In the Mode register the watchdog is defined and re-triggered, and the SBC operating
mode is selected. The Mode register also contains the global enable output bit (EN) and
the Software Development Mode (SDM) control bit. During system operation cyclic access
to the Mode register is required to serve the watchdog. This register can be written to in all
modes.
At system start-up the Mode register must be written to within t
WD(init)
from releasing
RSTN (HIGH-level on pin RSTN). Any write access is checked for proper watchdog and
system mode coding. If an illegal code is detected, access is ignored by the SBC and a
system reset is forced in accordance with the state diagram of the system controller; see
Figure 4.
Table 3. Register overview
Register
address bits
(A1, A0)
Operating
mode
Write access (RO = 0) Read access (RO = 0 or RO = 1)
Read Register Select
(RRS) bit = 0
Read Register Select
(RRS) bit = 1
00 all modes Mode register System Status register System Diagnosis register
01 Normal mode;
Standby mode;
Flash mode
Interrupt Enable register Interrupt Enable Feedback
register
Interrupt register
Start-up mode;
Restart mode
Special Mode register Interrupt Enable Feedback
register
Special Mode Feedback
register
10 Normal mode;
Standby mode
System Configuration
register
System Configuration
Feedback register
General Purpose Feedback
register 0
Start-up mode;
Restart mode;
Flash mode
General Purpose register 0 System Configuration
Feedback register
General Purpose Feedback
register 0
11 Normal mode;
Standby mode
Physical Layer Control
register
Physical Layer Control
Feedback register
General Purpose Feedback
register 1
Start-up mode;
Restart mode;
Flash mode
General Purpose register 1 Physical Layer Control
Feedback register
General Purpose Feedback
register 1
