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UJA1069TW/5V0/C/T,

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P64
UJA1069_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 28 October 2009 22 of 64
NXP Semiconductors
UJA1069
LIN fail-safe system basis chip
When pin INH/LIMP is used as inhibit output, a pull-down resistor to GND ensures a
default LOW level. The pin can be set to HIGH according to the state diagram.
When pin INH/LIMP is used as limp-home output, a pull-up resistor to V
BAT42
ensures a
default HIGH level. The pin is automatically set to LOW when the SBC enters Fail-safe
mode.
6.9 Wake-up input
The WAKE input comparator is triggered by negative edges on pin WAKE. Pin WAKE has
an internal pull-up resistor to BAT42. It can be operated in two sampling modes which are
selected via the WAKE Sample Control bit (WSC):
• Continuous sampling (with an internal clock) if the bit is set
• Sampling synchronized to the cyclic behavior of V3 if the bit is cleared; see Figure 13.
This is to save bias current within the external switches in low-power operation. Two
repetition times are possible, 16 ms and 32 ms.
If V3 is continuously ON, the WAKE input will be sampled continuously, regardless of the
level of bit WSC.
The dedicated bits Edge Wake-up Status (EWS) and WAKE Level Status (WLS) in the
System Status register reflect the actual status of pin WAKE. The WAKE port can be
disabled by clearing the WEN bit in the System Configuration register.
Fig 12. States of the INH/LIMP pin
001aad178
INH/LIMP:
HIGH
ILEN = 1
ILC = 1
INH/LIMP:
floating
ILEN = 0
ILC = 1/0
ILEN = 1
ILC = 0
INH/LIMP:
LOW
state change via SPI
state change via SPI
OR enter Fail-safe mode
state change via SPI
OR (enter Start-up mode after
wake-up reset, external reset
or V1 undervoltage)
OR enter Restart mode
OR enter Sleep mode
state change via SPI
power-on
state change via SPI
state change via SPI
OR enter Fail-safe mode
UJA1069_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 28 October 2009 23 of 64
NXP Semiconductors
UJA1069
LIN fail-safe system basis chip
6.10 Interrupt output
Pin INTN is an open-drain interrupt output. It is forced LOW whenever at least one bit in
the Interrupt register is set. By reading the Interrupt register all bits are cleared. The
Interrupt register will also be cleared during a system reset (RSTN LOW).
As the microcontroller operates typically with an edge-sensitive interrupt port, pin INTN
will be HIGH for at least t
INTN
after each read-out of the Interrupt register. Without further
interrupts within t
INTN
pin INTN stays HIGH, otherwise it will revert to LOW again.
To prevent the microcontroller from being slowed down by repetitive interrupts, in Normal
mode some interrupts are only allowed to occur once per watchdog period; see
Section 6.12.7.
If an interrupt is not read out within t
RSTN(INT)
a system reset is performed.
6.11 Temperature protection
The temperature of the SBC chip is monitored as long as the microcontroller voltage
regulator V1 is active. To avoid an unexpected shutdown of the application by the SBC,
the temperature protection will not switch off any part of the SBC or activate a defined
system stop of its own accord. If the temperature is too high it generates an interrupt to
the microcontroller, if enabled, and the corresponding status bit will be set. The
microcontroller can then decide whether to switch off parts of the SBC to decrease the
chip temperature.
Fig 13. Pin WAKE, cyclic sampling via V3
V
3
sample
active
V
WAKE
flip flop
V
INTN
t
on(CS)
t
w(CS)
t
su(CS)
approximately 70 %
signal already HIGH
due to biasing (history)
signal remains LOW
due to biasing (history)
button pushed button released
001aac307
UJA1069_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 28 October 2009 24 of 64
NXP Semiconductors
UJA1069
LIN fail-safe system basis chip
6.12 SPI interface
The Serial Peripheral Interface (SPI) provides the communication link with the
microcontroller, supporting multi-slave and multi-master operation. The SPI is configured
for full duplex data transfer, so status information is returned when new control data is
shifted in. The interface also offers a read-only access option, allowing registers to be
read back by the application without changing the register content.
The SPI uses four interface signals for synchronization and data transfer:
• SCS - SPI chip select; active LOW
• SCK - SPI clock; default level is LOW due to low-power concept
• SDI - SPI data input
• SDO - SPI data output; floating when pin SCS is HIGH
Bit sampling is performed on the falling clock edge and data is shifted on the rising clock
edge; see Figure 14.
To protect against wrong or illegal SPI instructions, the SBC detects the following SPI
failures:
• SPI clock count failure (wrong number of clock cycles during one SPI access): only
16 clock periods are allowed within one SCS cycle. Any deviation from the 16 clock
cycles results in an SPI failure interrupt, if enabled. The access is ignored by the SBC.
In Start-up and Restart mode a reset is forced instead of an interrupt
• Forbidden mode changes according to Figure 4 result in an immediate system reset
• Illegal Mode register code. Undefined operating mode or watchdog period coding
results in an immediate system reset; see Section 6.12.3
Fig 14. SPI timing protocol
SCS
SCK
01
sampled
floating floating
mce634
X
X
MSB 14 13 12 01 LSB
MSB 14 13 12 01 LSB
X
SDI
SDO
02 03 04 15 16
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P64

UJA1069TW/5V0/C/T,

Mfr. #:
Buy UJA1069TW/5V0/C/T,
Manufacturer:
NXP Semiconductors
Description:
LIN Transceivers IC LIN FAIL-SAFE
Lifecycle:
New from this manufacturer.
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