UJA1069_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 28 October 2009 47 of 64
NXP Semiconductors
UJA1069
LIN fail-safe system basis chip
[1] All parameters are guaranteed over the virtual junction temperature range by design. Products are 100 % tested at 125 °C ambient
temperature on wafer level (pretesting). Cased products are 100 % tested at 25 °C ambient temperature (final testing). Both pretesting
and final testing use correlated test conditions to cover the specified temperature and power supply voltage range.
[2] Not tested in production.
I
RTLIN(pu)
RTLIN pull-up
current
Active mode;
V
RTLIN
=V
LIN
=0V;
t>t
LIN(dom)(det)
−150 −60 −35 µA
Off-line mode;
V
RTLIN
=V
LIN
=0V;
t<t
LIN(dom)(det)
−150 −60 −35 µA
I
LL
LOW-level leakage
current
Off-line mode;
V
RTLIN
=V
LIN
=0V;
t>t
LIN(dom)(det)
−10 0 +10 µA
TEST input; pin TEST
V
th(TEST)
input threshold
voltage
for entering Software
development mode;
T
j
=25°C
158V
for entering Forced normal
mode; T
j
=25°C
2 10 13.5 V
R
(pd)TEST
pull-down resistor between pin TEST and GND 248kΩ
Temperature detection
T
j(warn)
high junction
temperature warning
level
160 175 190 °C
Table 25. Static characteristics
…continued
T
vj
=
−
40
°
C to +150
°
C, V
BAT42
=5.5Vto52V;V
BAT14
=5.5Vto27V;V
BAT42
≥
V
BAT14
−
1 V; unless otherwise specified. All
voltages are defined with respect to ground. Positive currents flow into the IC.
[1]
Symbol Parameter Conditions Min Typ Max Unit
