OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

UJA1069TW/5V0/C/T,

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P64
UJA1069_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 28 October 2009 34 of 64
NXP Semiconductors
UJA1069
LIN fail-safe system basis chip
[1] In case of an RXDL / TXDL interfacing failure the LIN transmitter is disabled without setting LTC. Recovery from such a failure is
automatic when LIN communication (with correct interfacing levels) is received. Manual recovery is also possible by setting and clearing
the LTC bit under software control.
6.12.10 Special Mode register and Special Mode Feedback register
These registers allow configuration of global SBC parameters during start-up of a system
and allow the settings to be read back.
12 RO Read Only 1 read the register selected by RRS without writing to the
Physical Layer Control register
0 read the register selected by RRS and write to Physical
Layer Control register
11 to 5 - reserved 000 0000 reserved for SBCs with CAN transceiver
4 LMC LIN Mode Control 1 LIN Active mode (in Normal mode and Flash mode only)
0 LIN Active mode disabled
3 LSC LIN Slope Control 1 up to 10.4 kbit/s (low slope)
0 up to 20 kbit/s (normal)
2 LDC LIN Driver Control 1 increased LIN driver current capability
0 LIN driver in conformance with the LIN 2.0 standard
1 - reserved 0 reserved for SBCs with CAN transceiver
0 LTC LIN Transmitter
Control
[1]
1 LIN transmitter is disabled
0 LIN transmitter is enabled
Table 11. Physical Layer Control and Physical Layer Control Feedback register bit description
…continued
Bit Symbol Description Value Function
Table 12. Special Mode register and Special Mode Feedback register bit description
Bit Symbol Description Value Function
15 and 14 A1, A0 register address 01 select Special Mode register
13 RRS Read Register Select 0 read the Interrupt Enable Feedback register
1 read the Special Mode Feedback register
12 RO Read Only 1 read the register selected by RRS without writing to the
Special Mode register
0 read the register selected by RRS and write to the
Special Mode register
11 and 10 - reserved 0 reserved for future use; should remain cleared to ensure
compatibility with future functions which might use this bit
9 ISDM Initialize Software
Development Mode
[1]
1 initialization of software development mode
0 normal watchdog interrupt, reset monitoring and fail-safe
behavior
8 - reserved 0 reserved for SBCs with CAN transceiver
7 - reserved 0 reserved for future use; should remain cleared to ensure
compatibility with future functions which might use this bit
6 and 5 WDPRE[1:0] Watchdog Prescaler 00 watchdog prescale factor 1
01 watchdog prescale factor 1.5
10 watchdog prescale factor 2.5
11 watchdog prescale factor 3.5
UJA1069_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 28 October 2009 35 of 64
NXP Semiconductors
UJA1069
LIN fail-safe system basis chip
[1] See Section 6.13.1.
6.12.11 General Purpose registers and General Purpose Feedback registers
The UJA1069 offers two 12-bit General Purpose registers (and accompanying General
Purpose Feedback registers) with no predefined bit definition. These registers can be
used by the microcontroller for advanced system diagnosis or for storing critical system
status information outside the microcontroller. After Power-up General Purpose register 0
will contain a ‘Device Identification Code’ consisting of the SBC type and SBC version.
This code is available until it is overwritten by the microcontroller (as indicated by the DIC
bit).
[1] The Device Identification Control bit is cleared during power-up of the SBC, indicating that General Purpose register 0 is loaded with the
Device Identification Code. Any write access to General Purpose register 0 will set the DIC bit, regardless of the value written to DIC.
[2] During power-up the General Purpose register 0 is loaded with a ‘Device Identification Code’ consisting of the SBC type and SBC
version, and the DIC bit is cleared.
4 and 3 V1RTHC[1:0] V1 Reset Threshold
Control
11 V1 reset threshold = 0.9 × V
V1(nom)
10 V1 reset threshold = 0.7 × V
V1(nom)
01 V1 reset threshold = 0.8 × V
V1(nom)
00 V1 reset threshold = 0.9 × V
V1(nom)
2 to 0 - reserved 000 reserved for future use; should remain cleared to ensure
compatibility with future functions which might use this bit
Table 12. Special Mode register and Special Mode Feedback register bit description
…continued
Bit Symbol Description Value Function
Table 13. General Purpose register 0 and General Purpose Feedback register 0 bit description
Bit Symbol Description Value Function
15, 14 A1, A0 register address 10 read the General Purpose Feedback register 0
13 RRS Read Register Select 1 read the General Purpose Feedback register 0
0 read the System Configuration Feedback register
12 RO Read Only 1 read the register selected by RRS without writing to the
General Purpose register 0
0 read the register selected by RRS and write to the General
Purpose register 0
11 DIC Device Identification
Control
[1]
1 General Purpose register 0 contains user-defined bits
0 General Purpose register 0 contains the Device
Identification Code
10 to 0 GP0[10:0] General Purpose bits
[2]
1 user-defined
0 user-defined
Table 14. General Purpose register 1 and General Purpose Feedback register 1 bit description
Bit Symbol Description Value Function
15 and 14 A1, A0 register address 11 select General Purpose register 1
13 RRS Read Register Select 1 read the General Purpose Feedback register 1
0 read the Physical Layer Control Feedback register
UJA1069_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 28 October 2009 36 of 64
NXP Semiconductors
UJA1069
LIN fail-safe system basis chip
6.12.12 Register configurations at reset
At Power-on, Start-up and Restart mode the setting of the SBC registers is predefined.
[1] Depends on history.
12 RO Read Only 1 read the register selected by RRS without writing to the
General Purpose register 1
0 read the register selected by RRS and write to the General
Purpose register
11 to 0 GP1[11:0] General Purpose bits 1 user-defined
0 user-defined
Table 14. General Purpose register 1 and General Purpose Feedback register 1 bit description
…continued
Bit Symbol Description Value Function
Table 15. System Status register: status at reset
Symbol Name Power-on Start-up
[1]
Restart
[1]
RSS Reset Source Status 0000 (power-on reset) any value except 1100 0000 or 0010 or 1100 or 1110
LWS LIN Wake-up Status 0 (no LIN wake-up) 1 if reset is caused by a
LIN wake-up, otherwise
no change
no change
EWS Edge Wake-up Status 0 (no edge detected) 1 if reset is caused by a
wake-up via pin WAKE,
otherwise no change
no change
WLS WAKE Level Status actual status actual status actual status
TWS Temperature Warning
Status
0 (no warning) actual status actual status
SDMS Software Development
Mode Status
actual status actual status actual status
ENS Enable Status 0 (EN = LOW) 0 (EN = LOW) 0 (EN = LOW)
PWONS Power-on Status 1 (power-on reset) no change no change
Table 16. System Diagnosis register: status at reset
Symbol Name Power-on Start-up Restart
LINFD LIN Failure Diagnosis 00 (no failure) actual status actual status
V3D V3 Diagnosis 1 (OK) actual status actual status
V1D V1 Diagnosis 0 (fail) actual status actual status
Table 17. Interrupt Enable register and Interrupt Enable Feedback register: status at reset
Symbol Name Power-on Start-up Restart
All all bits 0 (interrupt disabled) no change no change
Table 18. Interrupt register: status at reset
Symbol Name Power-on Start-up Restart
All all bits 0 (no interrupt) 0 (no interrupt) 0 (no interrupt)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P64

UJA1069TW/5V0/C/T,

Mfr. #:
Buy UJA1069TW/5V0/C/T,
Manufacturer:
NXP Semiconductors
Description:
LIN Transceivers IC LIN FAIL-SAFE
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet