UJA1069_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 28 October 2009 6 of 64
NXP Semiconductors
UJA1069
LIN fail-safe system basis chip
5.2 Pin description
Table 2. Pin description
Symbol Pin Description
HTSSOP32 HTSSOP24
n.c. 1 1 not connected
n.c. 2 - not connected
TXDL 3 2 LIN transmit data input (LOW for dominant, HIGH for
recessive)
V1 4 3 voltage regulator output for the microcontroller (5 V)
RXDL 5 4 LIN receive data output (LOW when dominant, HIGH
when recessive)
RSTN 6 5 reset output to microcontroller (active LOW; will detect
clamping situations)
INTN 7 6 interrupt output to microcontroller (active LOW;
open-drain, wire-AND this pin to other ECU interrupt
outputs)
EN 8 7 enable output (active HIGH; push-pull, LOW with every
reset / watchdog overflow)
SDI 9 8 SPI data input
SDO 10 9 SPI data output (floating when pin SCS is HIGH)
SCK 11 10 SPI clock input
SCS 12 11 SPI chip select input (active LOW)
n.c. 13 - not connected
n.c. 14 - not connected
n.c. 15 - not connected
TEST 16 12 test pin (should be connected to ground in application)
INH/LIMP 17 13 inhibit / limp home output (BAT14 related, push-pull,
default floating)
WAKE 18 14 local wake-up input (BAT42 related, continuous or cyclic
sampling)
n.c. 19 - not connected
n.c. 20 - not connected
n.c. 21 - not connected
n.c. 22 - not connected
GND 23 15 ground
n.c. 24 16 not connected
LIN 25 17 LIN bus line (LOW in dominant state)
RTLIN 26 18 LIN-bus termination resistor connection
BAT14 27 19 14 V battery supply input
n.c. 28 20 not connected
SYSINH 29 21 system inhibit output (BAT42 related; e.g. for controlling
external DC-to-DC converter)
