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UJA1069TW/5V0/C/T,

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P64
UJA1069_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 28 October 2009 31 of 64
NXP Semiconductors
UJA1069
LIN fail-safe system basis chip
[1] This bit is cleared automatically upon each overflow event. It has to be set in software each time the interrupt behavior is required
(fail-safe behavior).
[2] WEN (in the System Configuration register) has to be set to activate the WAKE port function globally.
6.12.7 Interrupt register
The Interrupt register allows the cause of an interrupt event to be read. The register is
cleared upon a read access and upon any reset event. Hardware ensures that no interrupt
event is lost in case there is a new interrupt forced while reading the register. After reading
the Interrupt register pin INTN is released for t
INTN
to guarantee an edge event at pin
INTN.
The interrupts can be classified into two groups:
• Timing critical interrupts which require immediate reaction (SPI clock count failure
which needs a new SPI command to be resent immediately, and a BAT failure which
needs critical data to be saved immediately into the nonvolatile memory)
• Interrupts which do not require an immediate reaction (overtemperature and LIN
failures, V1 and V3 failures and the wake-ups via LIN and WAKE. These interrupts will
be signalled in Normal mode to the microcontroller once per watchdog period
(maximum); this prevents overloading the microcontroller with unexpected interrupt
events (e.g. a chattering LIN failure). However, these interrupts are reflected in the
Interrupt register
7 BATFIE BAT Failure Interrupt
Enable
1 falling edge at SENSE forces an interrupt
0 no interrupt forced
6 VFIE Voltage Failure Interrupt
Enable
1 clearing of V1D or V3D forces an interrupt
0 no interrupt forced
5 - reserved 0 reserved for SBCs with CAN transceiver
4 LINFIE LIN Failure Interrupt
Enable
1 any change of the LIN Failure status bits forces an interrupt
0 no interrupt forced
3 WIE WAKE Interrupt
Enable
[2]
1 a negative edge at pin WAKE generates an interrupt in
Normal mode, Flash mode or Standby mode
0 a negative edge at pin WAKE generates a reset in Standby
mode; no interrupt in any other mode
2 WDRIE Watchdog Restart
Interrupt Enable
1 a watchdog restart during watchdog OFF generates an
interrupt
0 no interrupt forced
1 - reserved 0 reserved for SBCs with CAN transceiver
0 LINIE LIN Interrupt Enable 1 LIN-bus event results in a wake-up interrupt in Standby
mode and in Normal or Flash mode (unless LIN is in Active
mode already)
0 LIN-bus event results in a reset in Standby mode; no
interrupt in any other mode
Table 8. Interrupt Enable and Interrupt Enable Feedback register bit description
…continued
Bit Symbol Description Value Function
UJA1069_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 28 October 2009 32 of 64
NXP Semiconductors
UJA1069
LIN fail-safe system basis chip
6.12.8 System Configuration register and System Configuration Feedback register
These registers allow configuration of the behavior of the SBC, and allow the settings to
be read back.
Table 9. Interrupt register bit description
Bit Symbol Description Value Function
15 and 14 A1, A0 register address 01 read Interrupt register
13 RRS Read Register Select 1
12 RO Read Only 1 read the Interrupt register without writing to the Interrupt
Enable register
0 read the Interrupt register and write to the Interrupt Enable
register
11 WTI Watchdog Time-out
Interrupt
1 a watchdog overflow during Standby mode has caused an
interrupt (interrupt-based cyclic wake-up feature)
0 no interrupt
10 OTI OverTemperature
Interrupt
1 the temperature warning status (TWS) has changed
0 no interrupt
9 - reserved 0 reserved for SBCs with CAN transceiver
8 SPIFI SPI clock count Failure
Interrupt
1 wrong number of CLK cycles (more than, or less than 16)
during SPI access
0 no interrupt; SPI access is ignored if the number of CLK
cycles does not equal 16
7 BATFI BAT Failure Interrupt 1 falling edge at pin SENSE has forced an interrupt
0 no interrupt
6 VFI Voltage Failure Interrupt 1 V1D or V3D has been cleared
0 no interrupt
5 - reserved 0 reserved for SBCs with CAN transceiver
4 LINFI LIN Failure Interrupt 1 LIN failure status has changed
0 no interrupt
3 WI Wake-up Interrupt 1 a negative edge at pin WAKE has been detected
0 no interrupt
2 WDRI Watchdog Restart
Interrupt
1 A watchdog restart during watchdog OFF has caused an
interrupt
0 no interrupt
1 - reserved 0 reserved for SBCs with CAN transceiver
0 LINI LIN Wake-up Interrupt 1 LIN wake-up event has caused an interrupt
0 no interrupt
Table 10. System Configuration and System Configuration Feedback register bit description
Bit Symbol Description Value Function
15 and 14 A1, A0 register address 10 select System Configuration register
13 RRS Read Register Select 1 read the General Purpose Feedback register 0
0 read the System Configuration Feedback register
UJA1069_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 28 October 2009 33 of 64
NXP Semiconductors
UJA1069
LIN fail-safe system basis chip
[1] RLC is set automatically with entering Restart mode or Fail-safe mode. This guarantees a safe reset period in case of serious failure
situations. External reset spikes are lengthened by the SBC until the programmed reset length is reached.
[2] If WEN is not set, the WAKE port is completely disabled. There is no change of the bits EWS and WLS within the System Status
register.
6.12.9 Physical Layer Control register and Physical Layer Control Feedback
register
These registers allow configuration of the LIN transceiver of the SBC and allow the
settings to be read back.
12 RO Read Only 1 read register selected by RRS without writing to System
Configuration register
0 read register selected by RRS and write to System
Configuration register
11 and 10 - reserved 00 reserved for future use; should remain cleared to ensure
compatibility with future functions which might use this bit
9 - reserved 0 reserved for SBCs with CAN transceiver
8 RLC Reset Length Control 1
[1]
t
RSTNL
long reset lengthening time selected
0t
RSTNL
short reset lengthening time selected
7 and 6 V3C[1:0] V3 Control 11 Cyclic mode 2; t
w(CS)
long period; see Figure 13
10 Cyclic mode 1; t
w(CS)
short period; see Figure 13
01 continuously ON
00 OFF
5 - reserved 0 reserved for future use; should remain cleared to ensure
compatibility with future functions which might use this bit
4 V1CMC V1 Current Monitor
Control
1 an increasing V1 current causes a reset if the watchdog
was disabled in Standby mode
0 an increasing V1 current only reactivates the watchdog in
Standby mode
3 WEN Wake Enable
[2]
1 WAKE pin enabled
0 WAKE pin disabled
2 WSC Wake Sample Control 1 Wake mode cyclic sample
0 Wake mode continuous sample
1 ILEN INH/LIMP Enable 1 INH/LIMP pin active (See ILC bit)
0 INH/LIMP pin floating
0 ILC INH/LIMP Control 1 INH/LIMP pin HIGH if ILEN bit is set
0 INH/LIMP pin LOW if ILEN bit is set
Table 10. System Configuration and System Configuration Feedback register bit description
…continued
Bit Symbol Description Value Function
Table 11. Physical Layer Control and Physical Layer Control Feedback register bit description
Bit Symbol Description Value Function
15 and 14 A1, A0 register address 11 select Physical Layer Control register
13 RRS Read Register Select 1 read the General Purpose Feedback register 1
0 read the Physical Layer Control Feedback register
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P64

UJA1069TW/5V0/C/T,

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Manufacturer:
NXP Semiconductors
Description:
LIN Transceivers IC LIN FAIL-SAFE
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