UJA1069TW/5V0/C/T, Datasheet UJA1069TW24/5V0/C:, UJA1069TW/5V0/C/T,, UJA1069TW24/3V0,51 | P7-P9

Product data sheet Rev. 04 — 28 October 2009 7 of 64

NXP Semiconductors

UJA1069

LIN fail-safe system basis chip

The exposed die pad at the bottom of the package allows better dissipation of heat from

the SBC via the printed-circuit board. The exposed die pad is not connected to any active

part of the IC and can be left ﬂoating, or can be connected to GND for the best EMC

performance.

6. Functional description

6.1 Introduction

The UJA1069 combines all peripheral functions around a microcontroller within typical

automotive networking applications into one dedicated chip. The functions are as follows:

• Power supply for the microcontroller

• Switched BAT42 output

• System reset

• Watchdog with Window mode and Time-out mode

• On-chip oscillator

• LIN transceiver for serial communication

• SPI control interface

• Local wake-up input

• Inhibit or limp-home output

• System inhibit output port

• Compatibility with 42 V power supply systems

• Fail-safe behavior

6.2 Fail-safe system controller

The fail-safe system controller is the core of the UJA1069 and is supervised by a

watchdog timer which is clocked directly by the dedicated on-chip oscillator. The system

controller manages the register conﬁguration and controls all internal functions of the

SBC. Detailed device status information is collected and presented to the microcontroller.

The system controller also provides the reset and interrupt signals.

The fail-safe system controller is a state machine. The different operating modes and the

transitions between these modes are illustrated in Figure 4. The following sections give

further details about the SBC operating modes.

V3 30 22 unregulated 42 V output (BAT42 related; continuous

output, or cyclic mode synchronized with local wake-up

input)

SENSE 31 23 fast battery interrupt / chatter detector input

BAT42 32 24 42 V battery supply input (connect this pin to BAT14 in

14 V applications)

Table 2. Pin description

…continued

Symbol Pin Description

HTSSOP32 HTSSOP24

Product data sheet Rev. 04 — 28 October 2009 8 of 64

NXP Semiconductors

UJA1069

LIN fail-safe system basis chip

Fig 4. Main state diagram

001aad670

flash entry enabled (111/001/111 mode sequence)

OR mode change to Sleep with pending wake-up

OR watchdog not properly served

OR interrupt ignored > t

RSTN(INT)

OR RSTN falling edge detected

OR V1 undervoltage detected

OR illegal Mode register code

wake-up detected with its wake-up interrupt disabled

OR mode change to Sleep with pending wake-up

OR watchdog time-out with watchdog timeout interrupt disabled

OR watchdog OFF and I

> I

thH(V1)

with reset option

OR interrupt ignored > t

RSTN(INT)

OR RSTN falling edge detected

OR V1 undervoltage detected

OR illegal Mode register code

Start-up mode

V1: ON

SYSINH: HIGH

LIN: off-line

watchdog: start-up

INH/LIMP: HIGH/LOW/float

EN: LOW

Restart mode

V1: ON

SYSINH: HIGH

LIN: off-line

watchdog: start-up

INH/LIMP: LOW/float

EN: LOW

Sleep mode

V1: OFF

SYSINH: HIGH/float

LIN: off-line

watchdog: time-out/OFF

INH/LIMP: LOW/float

RSTN: LOW

EN: LOW

Fail-safe mode

V1: OFF

SYSINH: HIGH/float

LIN: off-line

watchdog: OFF

INH/LIMP: LOW

RSTN: LOW

EN: LOW

Normal mode

V1: ON

SYSINH: HIGH

LIN: all modes available

watchdog: window

INH/LIMP: HIGH/LOW/float

EN: HIGH/LOW

Flash mode

V1: ON

SYSINH: HIGH

LIN: all modes available

watchdog: time-out

INH/LIMP: HIGH/LOW/float

EN: HIGH/LOW

Standby mode

V1: ON

SYSINH: HIGH

LIN: off-line

watchdog: time-out/OFF

INH/LIMP: HIGH/LOW/float

EN: HIGH/LOW

mode change via SPImode change via SPI

mode change via SPI

wake-up detected

OR watchdog time-out

OR V3 overload detected

wake-up detected

AND oscillator ok

AND t > t

ret

t > t

WD(init)

OR SPI clock count <> 16

OR RSTN falling edge detected

OR RSTN released and V1 undervoltage detected

OR illegal Mode register code

t > t

WD(init)

OR SPI clock count <> 16

OR RSTN falling edge detected

OR RSTN released and V1 undervoltage detected

OR illegal Mode register code

leave Flash mode code

OR watchdog time-out

OR interrupt ignored > t

RSTN(INT)

OR RSTN falling edge detected

OR V1 undervoltage detected

OR illegal Mode register code

init Flash mode via SPI

AND flash entry enabled

init Normal mode

via SPI successful

init Normal mode

via SPI successful

supply connected

for the first time

from any

mode

oscillator fail

OR RSTN externally clamped HIGH detected > t

RSTN(CHT)

OR RSTN externally clamped LOW detected > t

RSTN(CLT)

OR V1 undervoltage detected > t

V1(CLT)

watchdog

trigger

watchdog

trigger

mode change via SPI

watchdog

trigger

Product data sheet Rev. 04 — 28 October 2009 9 of 64

NXP Semiconductors

UJA1069

LIN fail-safe system basis chip

6.2.1 Start-up mode

Start-up mode is the ‘home page’ of the SBC. This mode is entered when battery and

ground are connected for the ﬁrst time. Start-up mode is also entered after any event that

results in a system reset. The reset source information is provided by the SBC to support

different software initialization cycles that depend on the reset event.

It is also possible to enter Start-up mode via a wake-up from Standby mode, Sleep mode

or Fail-safe mode. Such a wake-up can originate either from the LIN-bus or from the local

WAKE pin.

On entering Start-up mode a lengthened reset time t

RSTNL

is observed. This reset time is

either user-deﬁned (via the RLC bit in the System Conﬁguration register) or defaults to the

value as given in Section 6.12.12. During the reset lengthening time pin RSTN is held

LOW by the SBC.

When the reset time is completed (pin RSTN is released and goes HIGH) the watchdog

timer will wait for initialization. If the watchdog initialization is successful, the selected

operating mode (Normal mode or Flash mode) will be entered. Otherwise the Restart

mode will be entered.

6.2.2 Restart mode

The purpose of the Restart mode is to give the application a second chance to start up,

should the ﬁrst attempt from Start-up mode fail. Entering Restart mode will always set the

reset lengthening time t

RSTNL

to the higher value to guarantee the maximum reset length,

regardless of previous events.

If start-up from Restart mode is successful (the previous problems do not reoccur and

watchdog initialization is successful), then the selected operating mode will be entered.

From Restart mode this must be Normal mode. If problems persist or if V1 fails to start up,

then Fail-safe mode will be entered.

6.2.3 Fail-safe mode

Severe fault situations will cause the SBC to enter Fail-safe mode. Fail-safe mode is also

entered if start-up from Restart mode fails. Fail-safe mode offers the lowest possible

system power consumption from the SBC and from the external components controlled by

the SBC.

A wake-up (via the LIN-bus or the WAKE pin) is needed to leave Fail-safe mode. This is

only possible if the on-chip oscillator is running correctly. The SBC restarts from Fail-safe

mode with a deﬁned delay t

ret

, to guarantee a discharged V1 before entering Start-up

mode. Regulator V1 will restart and the reset lengthening time t

RSTNL

is set to the higher

value; see Section 6.5.1.

6.2.4 Normal mode

Normal mode gives access to all SBC system resources, including LIN, INH/LIMP and

EN. Therefore in Normal mode the SBC watchdog runs in (programmable) Window mode,

for strictest software supervision. Whenever the watchdog is not properly served a system

reset is performed.

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UJA1069TW/5V0/C/T,

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LIN Transceivers IC LIN FAIL-SAFE

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