UJA1069_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 28 October 2009 52 of 64
NXP Semiconductors
UJA1069
LIN fail-safe system basis chip
Fig 22. V1 output stability related to ESR value of output capacitor
001aaf249
10
1
10
2
1
ESR
()
10
3
I
V1
(mA)
0 1208040
stable operation area
unstable operation area
UJA1069_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 28 October 2009 53 of 64
NXP Semiconductors
UJA1069
LIN fail-safe system basis chip
a. Test circuit
b. Behavior at T
j
=25°C
c. Behavior at T
j
=85°C
Fig 23. Switch-on behavior of V
V1
001aaf572
100
nF
100
nF
100 µF/
0.1
47 µF/
0.1
BAT42
BAT14
GND
V1
SBC
V
BAT
R
load
I
load
= 30 mA
015aaa095
t (ms)
0 2.01.60.8 1.20.4
2
4
6
V
V1
(V)
0
V
BAT
= 8 V
V
BAT
= 5.5 V
V
BAT
= 12 V
015aaa096
t (ms)
0 2.01.60.8 1.20.4
2
4
6
V
V1
(V)
0
V
BAT
= 8 V
V
BAT
= 5.5 V
V
BAT
= 12 V
UJA1069_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 28 October 2009 54 of 64
NXP Semiconductors
UJA1069
LIN fail-safe system basis chip
10. Dynamic characteristics
Table 26. Dynamic characteristics
T
vj
=
40
°
C to +150
°
C; V
BAT42
=5.5Vto52V;V
BAT14
=5.5Vto27V;V
BAT42
V
BAT14
1 V; unless otherwise specified. All
voltages are defined with respect to ground. Positive currents flow into the IC.
[1]
Symbol Parameter Conditions Min Typ Max Unit
Serial peripheral interface timing; pins SCS, SCK, SDI and SDO (see
Figure 24)
[2]
T
cyc
clock cycle time 960 - - ns
t
lead
enable lead time clock is low when SPI select
falls
240 - - ns
t
lag
enable lag time clock is low when SPI select
rises
240 - - ns
t
SCKH
clock HIGH time 480 - - ns
t
SCKL
clock LOW time 480 - - ns
t
su
input data setup time 80 - - ns
t
h
input data hold time 400 - - ns
t
DOV
output data valid time pin SDO; C
L
= 10 pF - - 400 ns
t
SSH
SPI select HIGH time 480 - - ns
LIN transceiver; pins LIN, TXDL and RXDL
[3]
δ1 duty cycle 1 V
th(reces)(max)
= 0.744 × V
BAT42
;
V
th(dom)(max)
= 0.581 × V
BAT42
;
LSC = 0; t
bit
=50µs;
V
BAT42
= 7 V to 18 V
[4]
0.396 - -
δ2 duty cycle 2 V
th(reces)(min)
= 0.422 × V
BAT42
;
V
th(dom)(min)
= 0.284 × V
BAT42
;
LSC = 0; t
bit
=50µs;
V
BAT42
= 7.6 V to 18 V
[5]
- - 0.581
δ3 duty cycle 3 V
th(reces)(max)
= 0.778 × V
BAT42
;
V
th(dom)(max)
= 0.616 × V
BAT42
;
LSC = 1; t
bit
=96µs;
V
BAT42
= 7 V to 18 V
[4]
0.417 - -
δ4 duty cycle 4 V
th(reces)(min)
= 0.389 × V
BAT42
;
V
th(dom)(min)
= 0.251 × V
BAT42
;
LSC = 1; t
bit
=96µs;
V
BAT42
= 7.6 V to 18 V
[5]
- - 0.590
t
p(rx)
propagation delay of
receiver
C
RXDL
=20pF - - 6 µs
t
p(rx)(sym)
symmetry of receiver
propagation delay
rising edge with respect to
falling edge; C
RXDL
=20pF
2-+2µs
t
BUS(LIN)
minimum dominant time for
wake-up of the
LIN-transceiver
Off-line mode 30 - 150 µs
t
LIN(dom)(det)
continuously dominant
clamped LIN-bus detection
time
Active mode; V
LIN
= 0 V 40 - 160 ms
t
LIN(dom)(rec)
continuously dominant
clamped LIN-bus recovery
time
Active mode 0.8 - 2.2 ms

UJA1069TW/5V0/C/T,

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
LIN Transceivers IC LIN FAIL-SAFE
Lifecycle:
New from this manufacturer.
Delivery:
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