UJA1069_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 28 October 2009 30 of 64
NXP Semiconductors
UJA1069
LIN fail-safe system basis chip
6.12.6 Interrupt Enable register and Interrupt Enable Feedback register
These registers allow setting, clearing and reading back the interrupt enable bits of the
SBC.
Table 7. System Diagnosis register bit description
Bit Symbol Description Value Function
15 and 14 A1, A0 register address 00 read System Diagnosis register
13 RRS Read Register Select 1
12 RO Read Only 1 read System Diagnosis register without writing to Mode
register
0 read System Diagnosis register and write to Mode register
11 to 7 - reserved 0 0000 reserved for SBCs with CAN transceiver
6 and 5 LINFD[1:0] LIN failure diagnosis 11 TXDL is clamped dominant
10 LIN is shorted to GND (dominant clamped)
01 LIN is shorted to VBAT (recessive clamped)
00 no failure
4 V3D V3 diagnosis 1 OK
0 fail; V3 is disabled due to an overload situation
3 - reserved 1 reserved for SBCs with another voltage regulator
2 V1D V1 diagnosis 1 OK; V1 always above V
UV(VFI)
since last read access
0 fail; V1 was below V
UV(VFI)
since last read access; bit is set
again with read access
1 and 0 - reserved 00 reserved for SBCs with CAN transceiver
Table 8. Interrupt Enable and Interrupt Enable Feedback register bit description
Bit Symbol Description Value Function
15 and 14 A1, A0 register address 01 select the Interrupt Enable register
13 RRS Read Register Select 1 read the Interrupt register
0 read the Interrupt Enable Feedback register
12 RO Read Only 1 read the register selected by RRS without writing to
Interrupt Enable register
0 read the register selected by RRS and write to Interrupt
Enable register
11 WTIE Watchdog Time-out
Interrupt Enable
[1]
1 a watchdog overflow during Standby causes an interrupt
instead of a reset event (interrupt based cyclic wake-up
feature)
0 no interrupt forced on watchdog overflow; a reset is forced
instead
10 OTIE Over-Temperature
Interrupt Enable
1 exceeding or dropping below the temperature warning limit
causes an interrupt
0 no interrupt forced
9 - reserved 0 reserved for SBCs with CAN transceiver
8 SPIFIE SPI clock count Failure
Interrupt Enable
1 wrong number of CLK cycles (more than, or less than 16)
forces an interrupt; from Start-up mode and Restart mode a
reset is performed instead of an interrupt
0 no interrupt forced; SPI access is ignored if the number of
cycles does not equal 16
