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1894K-40LFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P53
ICS1894-40
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER
IDT®
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 25
ICS1894-40 REV K 022412
20.11 LED3 Mode 000 = Link Integrity
001 = activity/no activity
010 = Transmit Data
011 = Receive Data
100 = Collision
101 = 100/10 mode
110 = Full Duplex
111 = OFF (Default LED3)
RW – 1
F
20.10 1
20.9 1
20.8 LED2 Mode 000 = Link Integrity
001 = activity/no activity
010 = Transmit Data
011 = Receive Data
100 = Collision
101 = 100/10 mode
110 = Full Duplex
111 = OFF (Default LED2)
RW 1
20.7 1
E
20.6 1
20.5 LED1 Mode 000 = Link Integrity
001 = activity/no activity
010 = Transmit Data
011 = Receive Data
100 = Collision
101 = 100/10 mode (Default LED1)
110 = Full Duplex
111 = OFF
RW 1
20.4 0
20.3 1
9
20.2 LED0 Mode 000 = Link Integrity
001 = activity/no activity (Default LED0)
010 = Transmit Data
011 = Receive Data
100 = Collision
101 = 100/10 mode
110 = Full Duplex
111 = LINK_STAT
RW 0
20.1 0
20.0 1
Register
21 - Extended Control Register
21.15:0 RXER_CNT Receive error count for RMII mode RW
0
Register 22 - Extended Control Register
22.15 Interrupt output enable Disable interrupt output Enable interrupt output RW 0
0
22.14 Interrupt flag read clear
enable
Interrupt flag clear by
read disable
Interrupt flag clear by read
enable
RW 0
22.13 Interrupt polarity Output low when
interrupt occur
Output high when
interrupt occur
RW 0
22.12 Interrupt flag auto clear
enable
Interrupt flag unchanged
when interrupt condition
removed
Interrupt flag cleared
when interrupt condition
removed
RW 0
Bit Definition When Bit = 0 When Bit = 1 Access
2
SF
2
Default
3
Hex
ICS1894-40
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER
IDT®
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 26
ICS1894-40 REV K 022412
22.11 Interrupt flag re-setup
enable
Interrupt flag always
cleared when write 1 to
flag bit
Interrupt flag remains
unchanged when
interrupt condition exists
when a 1 is written to flag
bit.
RW 0
0
22.10 Interrupt Enable Disable Deep power
down wake up Interrupt
Enable Deep power down
wake up Interrupt
RW 0
22.9 Interrupt Enable Disable Deep power
down Interrupt
Enable Deep power down
Interrupt
RW 0
22.8 Interrupt Enable Disable Auto-Negotiation
Complete Interrupt
Enable Auto-Negotiation
Complete Interrupt
RW 0
22.7 Interrupt Enable Disable Jabber Interrupt Enable Jabber Interrupt RW 0
0
22.6 Interrupt Enable Disable Receive Error
Interrupt
Enable Receive Error
Interrupt
RW 0
22.5 Interrupt Enable Disable Page Received
Interrupt
Enable Page Received
Interrupt
RW 0
22.4 Interrupt Enable Disable Parallel Detect
Fault Interrupt
Enable Parallel Detect
Fault Interrupt
RW 0
22.3 Interrupt Enable Disable Link Partner
Acknowledge Interrupt
Enable Link Partner
Acknowledge Interrupt
RW 0
0
22.2 Interrupt Enable Disable Link Down
Interrupt
Enable Link Down
Interrupt
RW 0
22.1 Interrupt Disable Remote Fault
Interrupt
Enable Remote Fault
Interrupt
RW 0
22.0 Enable Disable Link Up Interrupt Enable Link Up Interrupt RW 0
Register
23 - Extended Control Register
23.15:11 Reserved Reserved RO 0
0
23.10 Deep power down wake
up Interrupt
Deep power down wake
up did not occur
Deep power down wake
up occurred
RO/SC 0
0
23.9 Deep power down
Interrupt
Deep power down did
not occur
Deep power down
occurred
RO/SC 0
23.8 Auto-Negotiation
Interrupt
Auto-Negotiation
Complete did not occur
Auto-Negotiation
Complete occurred
RO/SC 0
23.7 Jabber Interrupt Jabber did not occur Jabber occurred RO/SC 0
0
23.6 Receive Error Interrupt Receive Error did not
occur
Receive Error occurred RO/SC 0
23.5 Page Receive Interrupt Page Receive did not
occur
Page Receive occurred RO/SC 0
23.4 Parallel Detect Fault
Interrupt
Parallel Detect Fault did
not occur
Parallel Detect Fault
occurred
RO/SC 0
Bit Definition When Bit = 0 When Bit = 1 Access
2
SF
2
Default
3
Hex
ICS1894-40
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER
IDT®
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 27
ICS1894-40 REV K 022412
23.3 Link Partner
Acknowledge Interrupt
Link Partner
Acknowledge did not
occur
Link Partner Acknowledge
occurred
RO/SC 0
0
23.2 Link Down Interrupt Link Down did not occur Link Down occurred RO/SC 0
23.1 Remote Fault Interrupt Remote Fault did not
occur
Remote Fault occurred RO/SC 0
23.0 Link Up Interrupt Link Up did not occur Link Up occurred RO/SC 0
Register 24 - Extended Control Register
24.15:12 FIFO Half RMII FIFO half full bits ((n+3)*2 bit), RMII RW 2 2
24.11:9 Reserved Reserved RW 0 0
24.8 Deep Power down
enable
Deep power down(DPD)
disable
Deep power down(DPD)
enable
RW 0
24.7 Tpll10_100 DPD Enable Don't power down
10/100 PLL in DPD
mode
Controlled auto power
down10/100 PLL in DPD
mode
RW 0 0
24.6 RX 100 DPD Enable Don't power down RX
block in DPD mode
Controlled auto power
down of RX block in DPD
mode
RW 0
24.5 Admix_TX DPD Enable Don't power down
admix_dac block in DPD
mode
Control auto power down
of admix_dac block in
DPD mode
RW 0
24.4 Cdr100_cdr DPD Enable don't power down in DPD
mod
Control auto power down
of CDR block in DPD
mode
RW 0
24.3:0 Reserved Reserved Reserved 00
Bit Definition When Bit = 0 When Bit = 1 Access
2
SF
2
Default
3
Hex
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P53

1894K-40LFT

Mfr. #:
Buy 1894K-40LFT
Manufacturer:
IDT
Description:
Ethernet ICs 3.3V 10/100 PHY RMII
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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