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1894K-40LFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P53
ICS1894-40
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER
IDT®
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 40
ICS1894-40 REV K 022412
100M / MII Media Independent Interface: Transmit Latency
The table below lists the significant time periods for the MII/100 Stream Interface transmit latency. The time periods
consist of timings of signals on the following pins:
• TXEN
• TXCLK
• TXD (that is, TXD[3:0])
• TP_TX (that is, TP_TXP and TP_TXN)
The MII/100M Stream Interface Transmit Latency Timing Diagram shows the timing diagram for the time periods.
† The IEEE maximum is 18 bit times.
MII/100M Stream Interface Transmit Latency Timing Diagram
Time
Period
Parameter Conditions Min. Typ. Max. Units
t1 TXEN Sampled to MDI Output of First
Bit of /J/ †
MII mode – 2.8 3 Bit times
TXEN
TXCLK
TXD
TP_TX
†
†
Shown
unscrambled.
t1
Preamble /K/Preamble /J/
ICS1894-40
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER
IDT®
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 41
ICS1894-40 REV K 022412
100M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission)
The table below lists the significant time periods for the 100M MII carrier assertion/de-assertion during half-duplex
transmission. The time periods consist of timings of signals on the following pins:
• TXEN
• TXCLK
• CRS
The 100M MII Carrier Assertion/De-Assertion Timing Diagram (Half-Duplex Transmission Only) shows the timing
diagram for the time periods.
100M MII Carrier Assertion/De-Assertion Timing Diagram (Half-Duplex Transmission Only)
Time
Period
Parameter Conditions Min. Typ. Max. Units
t1 TXEN Sampled Asserted to CRS Assert 0 3 4 Bit times
t2 TXEN De-Asserted to CRS De-Asserted 0 3 4 Bit times
t2
t1
TXEN
TXCLK
CRS
ICS1894-40
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER
IDT®
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 42
ICS1894-40 REV K 022412
10M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission)
The table below lists the significant time periods for the 10M MII carrier assertion/de-assertion during half-duplex
transmission. The time periods consist of timings of signals on the following pins:
• TXEN
• TXCLK
• CRS
The 10M MII Carrier Assertion/De-Assertion Timing Diagram (Half-Duplex Transmission Only) shows the timing diagram for
the time periods.
10M MII Carrier Assertion/De-Assertion Timing Diagram (Half-Duplex Transmission Only)
Time
Period
Parameter Conditions Min. Typ. Max. Units
t1 TXEN Asserted to CRS Assert 0 – 2 Bit times
t2 TXEN De-Asserted to CRS De-Asserted 0 2 4 Bit times
t2
t1
TXEN
TXCLK
CRS
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P53

1894K-40LFT

Mfr. #:
Buy 1894K-40LFT
Manufacturer:
IDT
Description:
Ethernet ICs 3.3V 10/100 PHY RMII
Lifecycle:
New from this manufacturer.
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