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1894K-40LFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P53
ICS1894-40
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER
IDT®
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 34
ICS1894-40 REV K 022412
Timing for Transmit Clock (TXCLK) Pin
The table below lists the significant time periods for signals on the Transmit Clock (TXCLK) pin. The Transmit Clock
Timing Diagram figure shows the timing diagram for the time periods.
Transmit Clock Timing Diagram
Timing for Receive Clock (RXCLK) Pin
The table below lists the significant time periods for signals on the Receive Clock (RXCLK) pin. The Receive Clock
Timing Diagram figure shows the timing diagram for the time periods.
Receive Clock Timing Diagram
Time
Period
Parameter Conditions Min. Typ. Max. Units
t1 TXCLK Duty Cycle – 35 50 65 %
t2a TXCLK Period 100M MII (100Base-TX) – 40 – ns
t2b TXCLK Period 10M MII (10Base-T) – 400 – ns
t1
t2x
TXCLK
Time
Period
Parameter Conditions Min. Typ. Max. Units
t1 RXCLK Duty Cycle – 35 50 65 %
t2a RXCLK Period 100M MII (100Base-TX) – 40 – ns
t2b RXCLK Period 10M MII (10Base-T) – 400 – ns
RXCLK
t1
t2
ICS1894-40
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER
IDT®
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 35
ICS1894-40 REV K 022412
100M MII: Synchronous Transmit Timing
The table below lists the significant time periods for the 100M MII Interface synchronous transmit timing. The time
periods consist of timings of signals on the following pins:
• TXCLK
• TXD[3:0]
• TXEN
• TXER
The 100M MII/100M Stream Interface Synchronous Transmit Timing Diagram figure shows the timing diagram for
the time periods.
100M MII/100M Stream Interface Synchronous Transmit Timing Diagram
10M MII: Synchronous Transmit Timing
The table below lists the significant time periods for the 10M MII synchronous transmit timing. The time periods
consist of timings of signals on the following pins:
• TXCLK
• TXD[3:0]
• TXEN
• TXER
The 10M MII Synchronous Transmit Timing Diagram figure shows the timing diagram for the time periods.
Time
Period
Parameter Conditions Min. Typ. Max. Units
t1 TXD[3:0], TXEN, TXER Setup to TXCLK Rise – 15 – – ns
t2 TXD[3:0], TXEN, TXER Hold after TXCLK Rise – 0 – – ns
t1 t2
TXCLK
TXD[3:0]
TXEN
TXER
Time
Period
Parameter Conditions Min. Typ. Max. Units
t1 TXD[3:0], TXEN, TXER Setup to TXCLK Rise – 375 – – ns
t2 TXD[3:0], TXEN, TXER Hold after TXCLK Rise – 0 – – ns
ICS1894-40
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER
IDT®
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 36
ICS1894-40 REV K 022412
10M MII Synchronous Transmit Timing Diagram
100M/MII Media Independent Interface: Synchronous Receive Timing
The table below lists the significant time periods for the MII/100M Stream Interface synchronous receive timing. The
time periods consist of timings of signals on the following pins:
• RXCLK
• RXD[3:0]
• RXDV
• RXER
The MII Interface: Synchronous Receive Timing figure shows the timing diagram for the time periods.
MII Interface: Synchronous Receive Timing
Time
Period
Parameter Min. Typ. Max. Units
t1 RXD[3:0], RXDV, and RXER Setup to RXCLK Rise 10.0 – – ns
t2 RXD[3:0], RXDV, and RXER Hold after RXCLK Rise 10.0 – – ns
t1 t2
TXCLK
TXD[3:0]
TXEN
TXER
t1 t2
RXCLK
RXD[3:0]
RXDV
RXER
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P53

1894K-40LFT

Mfr. #:
Buy 1894K-40LFT
Manufacturer:
IDT
Description:
Ethernet ICs 3.3V 10/100 PHY RMII
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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