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1894K-40LFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P53
ICS1894-40
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER
IDT®
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 4
ICS1894-40 REV K 022412
Notes:
1. AIO: Analog input/output PAD.
IO: Digital input/output.
IN/Ipu: Digital input with internal 20k pull-up.
IN/Ipd: Digital input with internal 20k pull-down.
IO/Ipu: Digital input/output with internal 20k pull-up.
IO/Ipd: Digital input/output with internal 20k pull-down.
2. MII Rx Mode: The RXD[3..0] bits are synchronous with RXCLK. When RXDV is asserted, RXD[3..0] presents
valid data to MAC on the MII interface. RXD[3..0] is invalid when RXDV is de-asserted.
3. RMII Rx Mode: The RXD[1:0] bits are synchronous with REFIN. For each clock period in which CRS_DV is
asserted, two bits of recovered data are sent from the PHY to the MAC.
4. MII Tx Mode: The TXD[3..0] bits are synchronous with TXCLK. When TXEN is asserted, TXD[3..0] presents valid
data from the MAC on the MII interface. TXD[3..0] has no effect when TXEN is de-asserted.
5. RMII Tx Mode: The TXD[1:0] bits are synchronous with REFIN. For each clock period in which TX_EN is
asserted, two bits of data are received by the PHY from the MAC.
28 SPEED/
TXCLK
IO/Ipu 10M/100M select as input (during power on reset and hardware reset)
Transmit clock as output in MII mode
29 TXEN Input Transmit enable for both RMII and MII modes
30 TXD0 Input Transmit data Bit 0 for both RMII and MII modes
31 VDDD Power Core Power Supply
32 LED3 IO/Ipu LED3 output
33 TXD1 Input Transmit data Bit 1for both RMII and MII modes
34 TXT2 Input Transmit data Bit 2 for MII mode
35 TXD3 Input Transmit data Bit 3 for MII mode
36 REF_OUT Output 25 MHz crystal output
37 REF_IN Input 25 MHz crystal (or clock) input for MII mode. 50MHz clock input for RMII mode
38 P4/LED2 IO/Ipu PHY address Bit 4 as input (always latched high during power on reset and
hardware reset) and LED # 2 as output
39 P0/LED0 IO PHY address Bit 0 as input (during power on reset and hardware reset) and LED #
0(function configurable, default is "activity/no activity") as output
40 P1/ISO/LED1 IO PHY address Bit 1 as input (during power on reset and hardware reset) and LED #
1 (function configurable, default is "10/100 mode") as output
Pin
Number
Pin
Name
Pin
Type
Pin Description
ICS1894-40
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER
IDT®
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 5
ICS1894-40 REV K 022412
Strapping Options
1. IO/Ipu = Digital Input with internal 20k pull-up during power on reset/hardware reset; output pin otherwise.
2. IO/Ipd = Digital Input with internal 20k pull-down during power on reset/hardware reset; output pin otherwise.
3. If RXTRI/RXD1 pin is latched high during power on reset/hardware reset, P1/ISO/LED1 functions as RX real time
isolation control input after latch and LED1 function will be disabled.
Functional Description
The ICS1894-40 is an ethernet PHYceiver. During data
transmission, it accepts sequential nibbles/di-bits from the
MAC (Media Access Control), converts them into a serial bit
stream, encodes them, and transmits them over the medium
through an external isolation transformer. When receiving
data, the ICS1894-40 converts and decodes a serial bit
stream (acquired from an isolation transformer that
interfaces with the medium) into sequential nibbles/di-bits. It
subsequently presents these nibbles/di-bits to the MAC
Interface.
Pin
Number
Pin
Name
Pin
Type
1
Pin Function
1 AMDIX IN/Ipu
1 = AMDIX enable
0 = AMDIX disable
16 HWSW/CRS IO/Ipd
Hardware pin select enable. Active during power-on and hardware reset.
17 REGPIN/COL IO/Ipd
Full register access enable. Active during power-on and hardware reset.
18 AMDIX/RXD2 IO/Ipu
1 = AMDIX enable
0 = AMDIX disable
38 P4/LED2 IO/Ipu The PHY address is set by P[4:0] at power-on reset. P0 and P1 must have external
pull-up or pull-down to set address at start up.
19 P3/RXD2 IO/Ipd
12 P2/INT IO/Ipd
40 P1/ISO/LED1 IO/
39 P0/LED0 IO/
21 SI/LED4 IO/Ipd MII/SI mode select.
Active during power-on and hardware reset.
20 RXTRI/RXD1 IO/Ipd
1=Realtime receiver isolation enable
3
;
0=RX output enable
22 FDPX/RXD0 IO/Ipu
1=Full duplex
0=Half duplex
Ignored if Auto negotiation is enabled
23 RMII/RXDV IO/Ipd
[1x]=RMII mode
[01]=SI mode (Serial interface mode)
[00]=MII mode
24 SPEED IO/Ipu
1=100M mode
0=10M mode
26 ANSEL/RXCLK IO/Ipu
1=Enable auto negotiation
0=Disable auto negotiation
27 NOD/RXER IO/Ipd
0=Node mode
1=repeater mode
28 SPEED/TXCLK IO/Ipu
1=100M mode
0=10M mode
Ignored if Auto negotiation is enabled
32 LED3 IO/Ipu LED3 output
ICS1894-40
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER
IDT®
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 6
ICS1894-40 REV K 022412
The ICS1894-40 implements the OSI model’s physical
layer, consisting of the following, as defined by the ISO/IEC
8802-3 standard:
• Physical Coding sublayer (PCS)
• Physical Medium Attachment sublayer (PMA)
• Physical Medium Dependent sublayer (PMD)
• Auto-Negotiation sublayer
The ICS1894-40 is transparent to the next layer of the OSI
model, the link layer. The link layer has two sublayers: the
Logical Link Control sublayer and the MAC sublayer. The
ICS1894-40 can interface directly with the MAC via MII/RMII
interface signals.
The ICS1894-40 transmits framed packets acquired from its
MAC Interface and receives encapsulated packets from
another PHY, which it translates and presents to its MAC
Interface.
Note: As per the ISO/IEC standard, the
ICS1894-40 does not affect, nor is it
affected by, the underlying structure of the
MAC frame it is conveying.
100Base-TX Operation
During 100Base-TX data transmission, the ICS1894-40
accepts packets from the MAC and inserts Start-of-Stream
Delimiters (SSDs) and End-of-Stream Delimiters (ESDs)
into the data stream. The ICS1894-40 encapsulates each
MAC frame, including the preamble, with an SSD and an
ESD. As per the ISO/IEC Standard, the ICS1894-40
replaces the first octet of each MAC preamble with an SSD
and appends an ESD to the end of each MAC frame.
When receiving data from the medium, the ICS1894-40
removes each SSD and replaces it with the pre-defined
preamble pattern before presenting the data on the MAC
Interface. When the ICS1894-40 encounters an ESD in the
received data stream, signifying the end of the frame, it ends
the presentation of data on the MAC Interface. Therefore,
the local MAC receives an unaltered copy of the transmitted
frame sent by the remote MAC.
During periods when MAC frames are being neither
transmitted nor received, the ICS1894-40 signals and
detects the IDLE condition on the Link Segment. In the
100Base-TX mode, the ICS1894-40 transmit channel sends
a continuous stream of scrambled ones to signify the IDLE
condition. Similarly, the ICS1894-40 receive channel
continually monitors its data stream and looks for a pattern
of scrambled ones. The results of this signaling and
monitoring provide the ICS1894-40 with the means to
establish the integrity of the Link Segment between itself
and its remote link partner and inform its Station
Management Entity (SME) of the link status.
10Base-T Operation
During 10Base-T data transmission, the ICS1894-40 inserts
only the IDL delimiter into the data stream. The ICS1894-40
appends the IDL delimiter to the end of each MAC frame.
However, since the 10Base-T preamble already has a
Start-of-Frame delimiter (SFD), it is not required that the
ICS1894-40 insert an SSD-like delimiter.
When receiving data from the medium (such as a
twisted-pair cable), the ICS1894-40 uses the preamble to
synchronize its receive clock. When the ICS1894-40
receive clock establishes lock, it presents the preamble
nibbles to the MAC Interface.
In 10M operations, during periods when MAC frames are
being neither transmitted nor received, the ICS1894-40
signals and detects Normal Link Pulses. This action allows
the integrity of the Link Segment with the remote link partner
to be established and then reported to the ICS1894-40’s
SME.
Auto-Negotiation
The ICS1894-40 conforms to the auto-negotiation protocol,
defined in Clause 28 of the IEEE 802.3u specification.
Autonegotiation is enabled by either hardware pin strapping
(pin 20) or software (register 0h bit 12).
Auto-negotiation allows link partners to select the highest
common mode of operation. Link partners advertise their
capabilities to each other, and then compare their own
capabilities with those they received from their link partners.
The highest speed and duplex setting that is common to the
two link partners is selected as the mode of operation.
The following list shows the speed and duplex operation
mode from highest to lowest.
• Priority 1: 100Base-TX, full-duplex
• Priority 2: 100Base-TX, half-duplex
• Priority 3: 10Base-T, full-duplex
• Priority 4: 10Base-T, half-duplex
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P53

1894K-40LFT

Mfr. #:
Buy 1894K-40LFT
Manufacturer:
IDT
Description:
Ethernet ICs 3.3V 10/100 PHY RMII
Lifecycle:
New from this manufacturer.
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