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SC28L92A1BS,551

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P73
SC28L92_7 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 07 — 19 December 2007 10 of 73
NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
TxDA 33 28 30 O Channel A transmitter serial data output: The least significant bit is
transmitted first. This output is held in the Mark condition when the
transmitter is disabled, Idle or when operating in local loopback mode.
See note on drive levels at block diagram (
Figure 1).
TxDB 13 6 8 O Channel B transmitter serial data output: The least significant bit is
transmitted first. This output is held in the Mark condition when the
transmitter is disabled, Idle, or when operating in local loopback mode.
See note on drive levels at block diagram (
Figure 1).
OP0 32 27 29 O Output 0: General purpose output or channel A request to send
(RTSAN, active LOW). Can be deactivated automatically on receive or
transmit.
OP1 14 7 9 O Output 1: General-purpose output or channel B request to send
(RTSBN, active LOW). Can be deactivated automatically on receive or
transmit.
OP2 31 26 28 O Output 2: General purpose output, or channel A transmitter 1× or 16×
clock output, or channel A receiver 1× clock output.
OP3 15 8 10 O Output 3: General purpose output or open-drain, active LOW
counter/timer output or channel B transmitter 1× clock output, or
channel B receiver 1× clock output.
OP4 30 25 27 O Output 4: General purpose output or channel A open-drain, active
LOW, RxA interrupt ISR[1] output.
OP5 16 9 11 O Output 5: General-purpose output or channel B open-drain, active
LOW, RxB interrupt ISR[5] output.
OP6 29 24 26 O Output 6: General purpose output or channel A open-drain, active
LOW, TxA interrupt ISR[0] output.
OP7 17 10 12 O Output 7: General-purpose output, or channel B open-drain, active
LOW, TxB interrupt ISR[4] output.
IP0 8 2 2 I Input 0: General purpose input or channel A clear to send active LOW
input (CTSAN).
IP1 5 43 47 I Input 1: General purpose input or channel B clear to send active LOW
input (CTSBN).
IP2 40 34 38 I Input 2: General-purpose input or counter/timer external clock input.
IP3 3 41 45 I Input 3: General purpose input or channel A transmitter external clock
input (TxCA). When the external clock is used by the transmitter, the
transmitted data is clocked on the falling edge of the clock.
IP4 43 37 41 I Input 4: General purpose input or channel A receiver external clock
input (RxCA). When the external clock is used by the receiver, the
received data is sampled on the rising edge of the clock.
IP5 42 36 40 I Input 5: General purpose input or channel B transmitter external clock
input (TxCB). When the external clock is used by the transmitter, the
transmitted data is clocked on the falling edge of the clock.
IP6 41 35 39 I Input 6: General purpose input or channel B receiver external clock
input (RxCB). When the external clock is used by the receiver, the
received data is sampled on the rising edge of the clock.
V
CC
44 38, 39 42 Pwr Power Supply: 3.3 V ± 10 % or 5 V ± 10 % supply input.
Table 2. Pin description for 80xxx bus interface (Intel)
…continued
Symbol Pin Type Description
PLCC44 QFP44 HVQFN48
SC28L92_7 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 07 — 19 December 2007 11 of 73
NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
[1] HVQFN48 package die supply ground is connected to both GND pin and exposed center pad. GND pin must be connected to supply
ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be
soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias
need to be incorporated in the PCB in the thermal pad region.
GND 22 16, 17 18
[1]
Pwr Ground
n.c. 1, 23, 34 23 6, 13, 24, 25,
36, 37, 43
Pwr Not connected
Table 2. Pin description for 80xxx bus interface (Intel)
…continued
Symbol Pin Type Description
PLCC44 QFP44 HVQFN48
Table 3. Pin description for 68xxx bus interface (Motorola)
Symbol Pin Type Description
PLCC44 QFP44 HVQFN48
I/M 12 11 7 I Bus configuration: When LOW configures the bus interface to the
conditions shown in this table.
D0 28 22 23 I/O Data bus: Bidirectional 3-state data bus used to transfer commands,
data and status between the DUART and the CPU. D0 is the least
significant bit.
D1 18 12 14 I/O
D2 27 21 22 I/O
D3 19 13 15 I/O
D4 26 20 21 I/O
D5 20 14 16 I/O
D6 25 19 20 I/O
D7 21 15 17 I/O
CEN 39 33 35 I Chip enable: Active LOW input signal. When LOW, data transfers
between the CPU and the DUART are enabled on D0 to D7 as
controlled by the R/WN and A0 to A3 inputs. When HIGH, places the
D0 to D7 lines in the 3-state condition.
R/WN 9 3 3 I Read/Write: Input signal. When CEN is LOW, R/WN HIGH input
indicates a read cycle; when LOW indicates a write cycle.
IACKN 41 35 39 I Interrupt acknowledge: Active LOW input indicating an interrupt
acknowledge cycle. Usually asserted by the CPU in response to an
interrupt request. When asserted places the interrupt vector on the
bus and asserts DACKN.
DACKN 10 4 4 O Data transfer acknowledge: A3-state active LOW output asserted in
a write, read, or interrupt acknowledge cycle to indicate proper
transfer of data between the CPU and the DUART.
A0 2 40 44 I Address inputs: Select the DUART internal registers and ports for
read/write operations.
A1 4 42 46 I
A2 6 44 48 I
A3 7 1 1 I
RESETN 38 32 34 I Reset: A LOW level clears internal registers (SRA, SRB, IMR, ISR,
OPR, OPCR), puts OP0 to OP7 in the HIGH state, stops the
counter/timer, and puts channels A and B in the inactive state, with the
TxDA and TxDB outputs in the mark (HIGH) state. Sets MR pointer to
MR1. See
Figure 10.
SC28L92_7 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 07 — 19 December 2007 12 of 73
NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
INTRN 24 18 19 O Interrupt request: Active LOW, open-drain, output which signals the
CPU that one or more of the eight maskable interrupting conditions
are true. This pin requires a pull-up.
X1/CLK 36 30 32 I Crystal 1: Crystal or external clock input. A crystal or clock of the
specified limits must be supplied at all times. When a crystal is used, a
capacitor must be connected from this pin to ground (see
Figure 17).
X2 37 31 33 O Crystal 2: Connection for other side of the crystal. When a crystal is
used, a capacitor must be connected from this pin to ground (see
Figure 17). If X1/CLK is driven from an external source, this pin must
be left open.
RxDA 35 29 31 I Channel A receiver serial data input: The least significant bit is
received first. See note on drive levels at block diagram (
Figure 2).
RxDB 11 5 5 I Channel B receiver serial data input: The least significant bit is
received first. See note on drive levels at block diagram (
Figure 2).
TxDA 33 28 30 O Channel A transmitter serial data output: The least significant bit is
transmitted first. This output is held in the ‘mark condition when the
transmitter is disabled, idle or when operating in local loopback mode.
See note on drive levels at block diagram (
Figure 2).
TxDB 13 6 8 O Channel B transmitter serial data output: The least significant bit is
transmitted first. This output is held in the Mark condition when the
transmitter is disabled, idle, or when operating in local loopback mode.
See note on drive levels at block diagram (
Figure 2).
OP0 32 27 29 O Output 0: General purpose output or channel A request to send
(RTSAN, active LOW). Can be deactivated automatically on receive or
transmit.
OP1 14 7 9 O Output 1: General purpose output or channel B request to send
(RTSBN, active LOW). Can be deactivated automatically on receive or
transmit.
OP2 31 26 28 O Output 2: General purpose output, or channel A transmitter 1× or 16×
clock output, or channel A receiver 1× clock output.
OP3 15 8 10 O Output 3: General purpose output or open-drain, active LOW
counter/timer output or channel B transmitter 1× clock output, or
channel B receiver 1× clock output.
OP4 30 25 27 O Output 4: General purpose output or channel A open-drain, active
LOW, RxA interrupt ISR [1] output.
OP5 16 9 11 O Output 5: General purpose output or channel B open-drain, active
LOW, RxB interrupt ISR[5] output.
OP6 29 24 26 O Output 6: General purpose output or channel A open-drain, active
LOW, TxA interrupt ISR[0] output.
OP7 17 10 12 O Output 7: General purpose output, or channel B open-drain, active
LOW, TxB interrupt ISR[4] output.
IP0 8 2 2 I Input 0: General purpose input or channel A clear to send active LOW
input (CTSAN).
IP1 5 43 47 I Input 1: General purpose input or channel B clear to send active LOW
input (CTSBN).
IP2 40 34 38 I Input 2: General purpose input or counter/timer external clock input.
Table 3. Pin description for 68xxx bus interface (Motorola)
…continued
Symbol Pin Type Description
PLCC44 QFP44 HVQFN48
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P73

SC28L92A1BS,551

Mfr. #:
Buy SC28L92A1BS,551
Manufacturer:
NXP Semiconductors
Description:
IC UART DUAL W/FIFO 48HVQFN
Lifecycle:
New from this manufacturer.
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