SC28L92A1BS,551 Datasheet SC28L92A1B,551, SC28L92A1B,528, SC28L92A1BS,551 | P13-P15

Product data sheet Rev. 07 — 19 December 2007 13 of 73

NXP Semiconductors

SC28L92

3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter

[1] HVQFN48 package die supply ground is connected to both GND pin and exposed center pad. GND pin must be connected to supply

ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be

soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias

need to be incorporated in the PCB in the thermal pad region.

6. Functional description

6.1 Block diagram

The SC28L92 DUART consists of the following eight major sections: data bus buffer,

operation control, interrupt control, timing, communications channels A and B, input port

and output port. Refer to Section 4 “Block diagram”.

6.1.1 Data bus buffer

The data bus buffer provides the interface between the external and internal data buses. It

is controlled by the operation control block to allow read and write operations to take place

between the controlling CPU and the DUART.

6.1.2 Operation control

The operation control logic receives operation commands from the CPU and generates

appropriate signals to internal sections to control device operation. It contains address

decoding and read and write circuits to permit communications with the microprocessor

via the data bus.

6.1.3 Interrupt control

A single active LOW interrupt output (INTRN) is provided which is activated upon the

occurrence of any of eight internal events. Associated with the interrupt system are the

Interrupt Mask Register (IMR) and the Interrupt Status Register (ISR). The IMR can be

programmed to select only certain conditions to cause INTRN to be asserted. The ISR

can be read by the CPU to determine all currently active interrupting conditions. Outputs

OP3 to OP7 can be programmed to provide discrete interrupt outputs for the transmitter,

IP3 3 41 45 I Input 3: General purpose input or channel A transmitter external clock

input (TxCA). When the external clock is used by the transmitter, the

transmitted data is clocked on the falling edge of the clock.

IP4 43 37 41 I Input 4: General purpose input or channel A receiver external clock

input (RxCA). When the external clock is used by the receiver, the

received data is sampled on the rising edge of the clock.

IP5 42 36 40 I Input 5: General purpose input or channel B transmitter external clock

input (TxCB). When the external clock is used by the transmitter, the

transmitted data is clocked on the falling edge of the clock.

44 38, 39 42 Pwr Power Supply: 3.3 V ± 10 % or 5 V ± 10 % supply input.

GND 22 16, 17 18

[1]

Pwr Ground

n.c. 1, 23, 34 23 6, 13, 24,

25, 36, 37,

- Not connected

Table 3. Pin description for 68xxx bus interface (Motorola)

…continued

Symbol Pin Type Description

PLCC44 QFP44 HVQFN48

Product data sheet Rev. 07 — 19 December 2007 14 of 73

NXP Semiconductors

SC28L92

3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter

receivers, and counter/timer. When OP3 to OP7 are programmed as interrupts, their

output buffers are changed to the open-drain active LOW conﬁguration. The OP pins may

be used for DMA and modem control as well (see Section 7.4).

6.1.4 FIFO conﬁguration

Each receiver and transmitter has a 16 byte FIFO. These FIFOs may be conﬁgured to

operate at a ﬁll capacity of either 8 bytes or 16 bytes. This feature may be used if it is

desired to operate the SC28L92 in strict compliance with the SC26C92. The 8 byte or

16 byte mode is controlled by the MR0A[3] bit. A logic 0 value for this bit sets the 8-bit

mode (the default); a logic 1 sets the 16 byte mode. MR0A bit 3 sets the FIFO size for both

channels.

The FIFO ﬁll interrupt level automatically follow the programming of the MR0A[3] bit. See

Table 25 and Table 26.

6.1.5 68xxx mode

When the I/M pin is connected to GND (ground), the operation of the SC28L92 switches to

the bus interface compatible with the Motorola bus interfaces. Several of the pins change

their function as follows:

IP6 becomes IACKN input

RDN becomes DACKN

WRN becomes R/WN

The interrupt vector is enabled and the interrupt vector will be placed on the data bus

when IACKN is asserted LOW. The interrupt vector register is located at address 0xC. The

contents of this register are set to 0x0F on the application of RESETN.

The generation of DACKN uses two positive edges of the X1 clock as the DACKN delay

from the falling edge of CEN. If the CEN is withdrawn before two edges of the X1 clock

occur, the generation of DACKN is terminated. Systems not strictly requiring DACKN

may use the 68xxx mode with the bus timing of the 80xxx mode greatly decreasing the

bus cycle time.

6.2 Timing circuits

6.2.1 Crystal clock

The timing block consists of a crystal oscillator, a baud rate generator, a programmable

16-bit counter/timer, and four clock selectors. The crystal oscillator operates directly from

a crystal connected across the X1/CLK and X2 inputs. If an external clock of the

appropriate frequency is available, it may be connected to X1/CLK. The clock serves as

the basic timing reference for the Baud Rate Generator (BRG), the counter/timer, and

other internal circuits. A clock signal within the limits speciﬁed in Section 10 “Dynamic

characteristics” must always be supplied to the DUART. If an external clock is used

instead of a crystal, X1 should be driven using a conﬁguration similar to the one in

Figure 17. Nominal crystal rate is 3.6864 MHz. Rates up to 8 MHz may be used.

Product data sheet Rev. 07 — 19 December 2007 15 of 73

NXP Semiconductors

SC28L92

3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter

6.2.2 Baud rate generator

The baud rate generator operates from the oscillator or external clock input at the X1 input

and is capable of generating 28 commonly used data communications baud rates ranging

from 50 kBd to 38.4 kBd. Programming bit 0 of MR0 to a logic 1 gives additional baud

rates of 57.6 kBd, 115.2 kBd and 230.4 kBd (500 kHz with X1 at 8.0 MHz). Note that the

MR0A[2:0] control this change and that the change applies to both channels. MR0B[2:0]

are reserved.

The baud rates are based on an input frequency of 3.6864 MHz. Changing the X1

frequency will change all baud rates by ratio of 3.6864 MHz to the new frequency. All rates

generated by the BRG will be in the 16× mode. The clock outputs from the BRG are at 16×

the actual baud rate.

The counter/timer can be used as a timer to produce a 16× clock for any other baud rate

by counting down the crystal clock or an external clock. The four clock selectors allow the

independent selection, for each receiver and transmitter, of any of these baud rates or

external timing signal. The use of the counter/timer also requires the generation of a

frequency 16× of the baud rate. See Section 6.2.3.

6.2.3 Counter/timer

The Counter/timer is a 16-bit programmable divider that operates in one of three modes:

counter, timer and time-out. In the timer mode it generates a square wave. In the counter

mode it generates a time delay. In the time-out mode it monitors the time between

received characters. The C/T uses the numbers loaded into the Counter/Timer Lower

The counter/timer clock source and mode of operation (counter or timer) is selected by the

Auxiliary Control Register bits 6 to 4 (ACR[6:4]). The output of the counter/timer may be

used for a baud rate and/or may be output to the OP pins for some external function that

may be totally unrelated to data transmission. The counter/timer also sets the

counter/timer ready bit in the Interrupt Status Register (ISR) when its output transitions

from logic 1 to logic 0. A register read address (see Table 4) is reserved to issue a start

counter/timer command and a second register read address is reserved to issue a stop

command. The value of D[7:0] is ignored. The START command always loads the

contents of CTUR, CTLR to the counting registers. The STOP command always resets

the ISR[3] bit in the interrupt status register.

6.2.4 Timer mode

In the timer mode a symmetrical square wave is generated whose half period is equal in

time to division of the selected counter/timer clock frequency by the 16-bit number loaded

in the CTLR CTUR. Thus, the frequency of the counter/timer output will be equal to the

counter/timer clock frequency divided by twice the value of the CTUR CTLR. While in the

timer mode the ISR bit 3 (ISR[3]) will be set each time the counter/timer transitions from

logic 1 to logic 0 (HIGH-to-LOW). This continues regardless of issuance of the stop

counter command. ISR[3] is reset by the stop counter command.

Note: Reading of the CTU and CTL registers in the timer mode is not meaningful. When

the C/T is used to generate a baud rate and the C/T is selected through the CSR then the

receivers and/or transmitter will be operating in the 16× mode. Calculation for the

number n to program the counter/timer upper and lower registers is shown in Equation 1.

The value of the divisor n is

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SC28L92A1BS,551

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IC UART DUAL W/FIFO 48HVQFN

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