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SC28L92A1BS,551

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P73
SC28L92_7 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 07 — 19 December 2007 61 of 73
NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
The test for open-drain outputs is intended to guarantee switching of the output transistor.
Measurement of this response is referenced from the midpoint of the switching signal, V
M
,toa
point 0.2 V above V
OL
. This point represents noise margin that assures true switching has
occurred. Beyond this level, the effects of external circuitry and test environment are
pronounced and can greatly affect the resultant measurement.
(1) IRQN or OP3 to OP7 when used as interrupt outputs.
Fig 16. Interrupt timing (80xxx mode)
WRN
RDN
V
M
interrupt output
(1)
V
OL
+ 0.5 V
V
OL
t
IR
V
M
V
OL
+ 0.5 V
V
OL
interrupt output
(1)
001aae313
t
IR
SC28L92_7 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 07 — 19 December 2007 62 of 73
NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
C1 = C2 ∼ 24 pF for C
L
= 13.5 pF. For the oscillator feedback loop, the capacitors C1 and C2 are in series.
C1 and C2 should be chosen according to the crystal manufacturer’s specification.
C1 and C2 values will include any parasitic capacitance of the wiring and X1, X2 pins.
Package capacitance approximately 4 pF.
Fig 17. Clock timing
CLK
X2
3.6864 MHz
X1
C1
C2
SC28L92
2 pF
4 pF
X1/CLK
C/T clock
RxC
TxC
t
CLK
t
CTC
t
RX
t
TX
t
CLK
t
CTC
t
RX
t
TX
X1
X2
(must be left open)
V
CC
470 Ω
resistor required
for TTL input
001aae314
to UART circuit
50 kΩ
to
100 kΩ
3 pF
parasitic capacitance
3 pF
parasitic capacitance
Fig 18. Transmitter external clocks
Fig 19. Receiver external clock
001aae315
1 bit time
(1 or 16 clocks)
TxC
(input)
TxD
t
TXD
TxC
(1× output)
t
TCS
001aae316
RxD
RxC
(1× input)
t
RXS
t
RXH
SC28L92_7 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 07 — 19 December 2007 63 of 73
NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
(1) Timing shown for MR2[4] = 1.
(2) Timing shown for MR2[5] = 1.
Fig 20. Transmitter timing
D1 D2 D3 D4 D6
D1 D8 D9 D10 D12
OPR(0) = 1 OPR(0) = 1
001aae317
D11 will not
be written to
the TxFIFO
RTSN
(2)
(OP0)
CTSN
(1)
(IP0)
start
break
stop
break
WRN
TxRDY
(SR2)
transmitter
enabled
TxD
break
(1) Timing shown for MR1[7] = 1.
(2) Shown for OPCR[4] = 1 and MR[6] = 0.
Fig 21. Receiver timing
D1 D2 D8 D9 D10 D11 D12 D13
RDN
D1 D2 D3 D10
OPR[0] = 1
001aae318
RTS
(1)
(OP0)
OVERRUN
(SR)
reset by command
status data
status data
D11 will be lost
due to overrun
status data status data
RxRDY/
FFULL
(OP5)
(2)
FFULL
(CR)
RxRDY
(SR)
receiver
enabled
D12, D13 will be lost
due to receiver disable
RxD
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P73

SC28L92A1BS,551

Mfr. #:
Buy SC28L92A1BS,551
Manufacturer:
NXP Semiconductors
Description:
IC UART DUAL W/FIFO 48HVQFN
Lifecycle:
New from this manufacturer.
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