SC28L92_7 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 07 — 19 December 2007 33 of 73
NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
7.3.2 Clock select registers
7.3.2.1 Clock Select Register channel A (CSRA)
Table 33. CSRA - Clock select register channel A (address 0x1) and
CSRB - Clock select register channel B (address 0x9) bit allocation
7 6 5 4 3 2 1 0
receiver clock select code transmitter clock select code
Table 34. CSRA - Clock select register channel A (address 0x1) bit description
Bit Symbol Description
7 to 4 - Receiver clock select. The baud rate clock for the channel A receiver is as
shown in
Table 35, except as follows:
1110 = IP4 - 16×
1111 = IP4 - 1×
The receiver clock is always a 16× clock except for CSRA[7:4] = 1111
3 to 0 - Transmitter clock select. The baud rate clock for the channel A transmitter is
as shown in
Table 35, except as follows:
1110 = IP3 - 16×
1111 = IP3 - 1×
The transmitter clock is always a 16× clock except for CSRA[3:0] = 1111
Table 35. Baud rate (based on a 3.6864 MHz crystal clock)
See Table 36 for bit rate characteristics.
CSR[7:4]
CSR[3:0]
MR0[0] = 0 (Normal mode) MR0[0] = 1 (Extended mode I) MR0[2] = 1 (Extended mode II)
ACR[7] = 0 ACR[7] = 1 ACR[7] = 0 ACR[7] = 1 ACR[7] = 0 ACR[7] = 1
0000 50 75 300 450 4,800 7,200
0001 110 110 110 110 880 880
0010 134.5 134.5 134.5 134.5 1,076 1,076
0011 200 150 1200 900 19.200 14.400
0100 300 300 1800 1800 28.800 28.800
0101 600 600 3600 3600 57.600 57.600
0110 1,200 1,200 7200 7,200 115,200 115,200
0111 1,050 2,000 1,050 2,000 1,050 2,000
1000 2,400 2,400 14,400 14,400 57,600 57,600
1001 4,800 4,800 28,800 28,800 4,800 4,800
1010 7,200 1,800 7,200 1,800 57,600 14,400
1011 9,600 9,600 57,600 57,600 9,600 9,600
1100 38,400 19,200 230,400 115,200 38,400 19,200
1101 Timer Timer Timer Timer Timer Timer
