SC28L92_7 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 07 — 19 December 2007 28 of 73
NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
7.3.1.2 Mode Register 1 channel A (MR1A)
[1] In block error mode, block error conditions must be cleared by using the error reset command (command 0x4) or a receiver reset.
Table 27. MR1A - Mode Register 1 channel A (address 0x0) bit allocation
MR1A is accessed when the channel A MR pointer points to MR1. The pointer is set to MR1 by RESET or by a set pointer
command applied via CR command 1. After reading or writing MR1A, the pointer will point to MR2A
[1]
.
7 6 5 4 3 2 1 0
RxRTS
control
RxINT[1] ERRORMODE PARITYMODE PARITYTYPE bits per character
Table 28. MR1A - Mode Register 1 channel A (address 0x0) bit description
Bit Symbol Description
7 RxRTS Channel A receiver request to send control (flow control). This bit
controls the deactivation of the RTSAN output (OP0) by the receiver.
This output is normally asserted by setting OPR[0] and negated by
resetting OPR[0]. Proper automatic operation of flow control requires
OPR[0] (channel A) or OPR[1] (channel B) to be set to logic 1.
0 = No RTS control
1 = RTS control
RxRTS = 1 causes RTSAN to be negated (OP0 is driven to a
logic 1 [V
CC
]) upon receipt of a valid start bit if the channel A FIFO is
full. This is the beginning of the reception of the 9th byte. If the FIFO is
not read before the start of the 10th or 17th byte, an overrun condition
will occur and the 10th or 17th or 17th byte will be lost. However, the
bit in OPR[0] is not reset and RTSAN will be asserted again when an
empty FIFO position is available. This feature can be used for flow
control to prevent overrun in the receiver by using the RTSAN output
signal to control the CTSN input of the transmitting device.
6 RxINT[1] Bit 1 of the receiver interrupt control. See description of RxINT[2] in
Table 25 and Table 26.
5 ERRORMODE Channel A error mode select.
0 = character
1 = block
This bit selects the operating mode of the three FIFOed status bits
(FE, PE, received break) for channel A. In the character mode, status
is provided on a character-by-character basis; the status applies only
to the character at the top of the FIFO. In the block mode, the status
provided in the SR for these bits is the accumulation (logic OR) of the
status for all characters coming to the top of the FIFO since the last
reset error command for channel A was issued.
4 and 3 PARITYMODE Channel A parity mode select
00 = with parity
01 = force parity
10 = no parity
11 = multi-drop special mode
If with parity or force parity is selected a parity bit is added to the
transmitted character and the receiver performs a parity check on
incoming data MR1A[4:3] = 11 selects channel A to operate in the
special multi-drop mode described in
Section 6.3.10 “Multi-drop mode
(9-bit or wake-up)”.
