SC28L92_7 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 07 — 19 December 2007 22 of 73
NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
6.3.9 Time-out mode caution
When operating in the special time-out mode, it is possible to generate what appears to be
a false interrupt, i.e., an interrupt without a cause. This may result when a time-out
interrupt occurs and then, before the interrupt is serviced, another character is received,
i.e., the data stream has started again. (The interrupt latency is longer than the pause in
the data stream.) In this case, when a new character has been receiver, the counter/timer
will be restarted by the receiver, thereby withdrawing its interrupt. If, at this time, the
interrupt service begins for the previously seen interrupt, a read of the ISR will show the
counter ready bit not set. If nothing else is interrupting, this read of the ISR will return a
0x00 character.
6.3.10 Multi-drop mode (9-bit or wake-up)
The DUART is equipped with a wake-up mode for multi-drop applications. This mode is
selected by programming bits MR1A[4:3] or MR1B[4:3] to 11 for channels A and B,
respectively. In this mode of operation, a master station transmits an address character
followed by data characters for the addressed slave station. The slave stations, with
receivers that are normally disabled, examine the received data stream and wake-up the
CPU (by setting RxRDY) only upon receipt of an address character. The CPU compares
the received address to its station address and enables the receiver if it wishes to receive
the subsequent data characters. Upon receipt of another address character, the CPU may
disable the receiver to initiate the process again.
A transmitted character consists of a start bit, the programmed number of data bits, and
Address/Data (A/D) bit, and the programmed number of stop bits. The polarity of the
transmitted A/D bit is selected by the CPU by programming bit MR1A[2]/MR1B[2].
MR1A[2]/MR1B[2] = 0 transmits a zero in the A/D bit position, which identifies the
corresponding data bits as data while MR1A[2]/MR1B[2] = 1 transmits a one in the A/D bit
position, which identifies the corresponding data bits as an address. The CPU should
program the mode register prior to loading the corresponding data bits into the Tx FIFO.
In this mode, the receiver continuously looks at the received data stream, whether it is
enabled or disabled. If disabled, it sets the RxRDY status bit and loads the character into
the Rx FIFO if the received A/D bit is a one (address tag), but discards the received
character if the received A/D bit is a zero (data tag). If enabled, all received characters are
transferred to the CPU via the Rx FIFO. In either case, the data bits are loaded into the
data FIFO while the A/D bit is loaded into the status FIFO position normally used for parity
error (SRA[5] or SRB[5]). Framing error, overrun error, and break detect operate normally
whether or not the receive is enabled.
7. Programming
7.1 Register overview
The operation of the DUART is programmed by writing control words into the appropriate
registers. Operational feedback is provided via status registers which can be read by the
CPU. The addressing of the registers is described in Table 4.
The contents of certain control registers are initialized to zero on RESET. Care should be
exercised if the contents of a register are changed during operation, since certain
changes may cause operational problems.
