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SC28L92A1BS,551

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P73
SC28L92_7 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 07 — 19 December 2007 37 of 73
NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
7.3.4 Status registers
7.3.4.1 Status Register channel A (SRA)
[1] These status bits are appended to the corresponding data character in the receive FIFO. A read of the
status provides these bits [7:5] from the top of the FIFO together with bits [4:0]. These bits are cleared by a
reset error status command. In character mode they are discarded when the corresponding data character
is read from the FIFO. In block error mode, the error-reset command (command 0x4 or receiver reset) must
used to clear block error conditions.
Table 41. SRA - Status register channel A (address 0x1) bit allocation
7 6 5 4 3 2 1 0
received
break
[1]
framing
error
[1]
parity
error
[1]
overrun
error
TxEMTA TxRDYA RxFULLA RxRDYA
Table 42. SRA - Status register channel A (address 0x1) bit description
Bit Symbol Description
7 - Channel A received break.
0 = no
1 = yes
This bit indicates that an all zero character of the programmed length has been
received without a stop bit. Only a single FIFO position is occupied when a
break is received: further entries to the FIFO are inhibited until the RxDA line
returns to the marking state for at least one-half a bit time two successive
edges of the internal or external 1× clock. This will usually require a HIGH
time of one X1 clock period or 3 X1 edges since the clock of the controller
is not synchronous to the X1 clock.
When this bit is set, the channel A change in break bit in the ISR (ISR[2]) is set.
ISR[2] is also set when the end of the break condition, as defined above, is
detected.
The break detect circuitry can detect breaks that originate in the middle of a
received character. However, if a break begins in the middle of a character, it
must persist until at least the end of the next character time in order for it to be
detected.
This bit is reset by command 0x4 (0100) written to the command register or by
receiver reset.
6 - Channel A framing error.
0 = no
1 = yes
This bit, when set, indicates that a stop bit was not detected (not a logic 1)
when the corresponding data character in the FIFO was received. The stop bit
check is made in the middle of the first stop bit position.
5 - Channel A parity error.
0 = no
1 = yes
This bit is set when the with parity or force parity mode is programmed and the
corresponding character in the FIFO was received with incorrect parity.
In the special multi-drop mode the parity error bit stores the receive A/D
(Address/Data) bit.
SC28L92_7 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 07 — 19 December 2007 38 of 73
NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
4 - Channel A overrun error.
0 = no
1 = yes
This bit, when set, indicates that one or more characters in the received data
stream have been lost. It is set upon receipt of a new character when the FIFO
is full and a character is already in the receive shift register waiting for an empty
FIFO position. When this occurs, the character in the receive shift register (and
its break detect, parity error and framing error status, if any) is lost.
This bit is cleared by a reset error status command.
3 TxEMTA Channel A transmitter empty.
0 = no
1 = yes
This bit will be set when the transmitter under runs, i.e., both the TxEMT and
TxRDY bits are set. This bit and TxRDY are set when the transmitter is first
enabled and at any time it is re-enabled after either (a) reset, or (b) the
transmitter has assumed the disabled state. It is always set after transmission
of the last stop bit of a character if no character is in the Tx Holding Register
(TxFIFOA) awaiting transmission.
It is reset when the Tx Holding Register (TxFIFOA) is loaded by the CPU, a
pending transmitter disable is executed, the transmitter is reset, or the
transmitter is disabled while in the under run condition.
2 TxRDYA Channel A transmitter ready.
0 = no
1 = yes
This bit, when set, indicates that the transmit FIFO is not full and ready to be
loaded with another character. This bit is cleared when the transmit FIFO is
loaded by the CPU and there are (after this load) no more empty locations in
the FIFO. It is set when a character is transferred to the transmit shift register.
TxRDYA is reset when the transmitter is disabled and is set when the
transmitter is first enabled. Characters loaded to the Tx FIFO while this bit is
logic 0 will be lost. This bit has different meaning from ISR[0].
1 FFULLA Channel A FIFO full.
0 = no
1 = yes
This bit is set when a character is transferred from the receive shift register to
the receive FIFO and the transfer causes the FIFO to become full, i.e., all eight
(or 16) FIFO positions are occupied. It is reset when the CPU reads the receive
FIFO. If a character is waiting in the receive shift register because the FIFO is
full, FFULLA will not be reset when the CPU reads the receive FIFO. This bit
has different meaning from ISR1 when MR1[6] is programmed to a logic 1
0 RxRDYA Channel A receiver ready.
0 = no
1 = yes
This bit indicates that a character has been received and is waiting in the FIFO
to be read by the CPU. It is set when the character is transferred from the
receive shift register to the FIFO and reset when the CPU reads the receive
FIFO, only if (after this read) there are no more characters in the FIFO - the Rx
FIFO becomes empty.
Table 42. SRA - Status register channel A (address 0x1) bit description
…continued
Bit Symbol Description
SC28L92_7 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 07 — 19 December 2007 39 of 73
NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
7.3.4.2 Status Register channel B (SRB)
[1] These status bits are appended to the corresponding data character in the receive FIFO. A read of the
status provides these bits [7:5] from the top of the FIFO together with bits [4:0]. These bits are cleared by a
reset error status command. In character mode they are discarded when the corresponding data character
is read from the FIFO. In block error mode, the error-reset command (command 0x4 or receiver reset) must
used to clear block error conditions.
The bit definitions for this register are identical to the bit definitions for SRA, except that all
status applies to the channel B receiver and transmitter and the corresponding inputs and
outputs.
7.3.5 Output Configuration Control Register (OPCR)
This register controls the signal presented by the OP[7:2] pins. The signal presented by
the OP[1:0] pins is controlled by the Rx, Tx, and the command register. The default
condition of the OP pins is to drive the complement of the data in the OPR[7:0] register.
When OP[7:2] pins drive DMA or interrupt type signals, they switch to open-drain
configuration. Otherwise, they drive strong logic 0 or logic 1 levels.
Table 43. SRB - Status register channel B (address 0x9) bit allocation
7 6 5 4 3 2 1 0
received
break
[1]
framing
error
[1]
parity
error
[1]
overrun
error
TxEMTB TxRDYB RxFULLB RxRDYB
Table 44. OPCR - Output configuration control register (address 0xD) bit allocation
7 6 5 4 3 2 1 0
configure
OP7
configure
OP6
configure
OP5
configure
OP4
configure OP3 configure OP2
Table 45. OPCR - Output configuration control register (address 0xD) bit description
Bit Symbol Description
7 - OP7 output select
0 = The complement of OPR[7]
1 = The channel B transmitter interrupt output which is the complement of
ISR[4]. When in this mode OP7 acts as an open-drain output. Note that
this output is not masked by the contents of the IMR.
6 - OP6 output select
0 = The complement of OPR[6]
1 = The channel A transmitter interrupt output which is the complement of
ISR[0]. When in this mode OP6 acts as an open-drain output. Note that
this output is not masked by the contents of the IMR.
5 - OP5 output select
0 = The complement of OPR[5]
1 = The channel B receiver interrupt output which is the complement of
ISR[5]. When in this mode OP5 acts as an open-drain output. Note that
this output is not masked by the contents of the IMR.
4 - OP4 output select
0 = The complement of OPR[4]
1 = The channel A receiver interrupt output which is the complement of
ISR[1]. When in this mode OP4 acts as an open-drain output. Note that
this output is not masked by the contents of the IMR.
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SC28L92A1BS,551

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Manufacturer:
NXP Semiconductors
Description:
IC UART DUAL W/FIFO 48HVQFN
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