SC28L92_7 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 07 — 19 December 2007 40 of 73
NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
3 and 2 - OP3 output select
00 = The complement of OPR[3]
01 = The counter/timer output, in which case OP3 acts as an open-drain
output. In the timer mode, this output is a square wave at the programmed
frequency. In the counter mode, the output remains HIGH until terminal
count is reached, at which time it goes LOW. The output returns to the
HIGH state when the counter is stopped by a stop counter command. Note
that this output is not masked by the contents of the IMR.
10 = The 1× clock for the channel B transmitter, which is the clock that
shifts the transmitted data. If data is not being transmitted, a free running
1× clock is output.
11 = The 1× clock for the channel B receiver, which is the clock that
samples the received data. If data is not being received, a free running 1×
clock is output.
1 and 0 - OP2 output select
00 = The complement of OPR[2]
01 = The 16× clock for the channel A transmitter. This is the clock selected
by CSRA[3:0], and will be a 1× clock if CSRA[3:0] = 1111.
10 = The 1× clock for the channel A transmitter, which is the clock that
shifts the transmitted data. If data is not being transmitted, a free running
1× clock is output.
11 = The 1× clock for the channel A receiver, which is the clock that
samples the received data. If data is not being received, a free running 1×
clock is output.
Table 45. OPCR - Output configuration control register (address 0xD) bit description
Bit Symbol Description
