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SC28L92A1BS,551

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P73
SC28L92_7 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 07 — 19 December 2007 19 of 73
NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
If CTS option is enabled (MR2[4] = 1), the CTS input at IP0 or IP1 must be LOW in order
for the character to be transmitted. The transmitter will check the state of the CTS input at
the beginning of each character transmitted. If it is found to be HIGH, the transmitter will
delay the transmission of any following characters until the CTS has returned to the LOW
state. CTS going HIGH during the serialization of a character will not affect that character.
The transmitter can also control the RTSN outputs, OP0 or OP1 via MR2[5]. When this
mode of operation is set, the meaning of the OP0 or OP1 signals will usually be end of
message. See description of bit MR2[5] in Table 30 “MR2A - Mode Register 2 channel A
(address 0x0) bit description” for more detail. This feature may be used to automatically
turn around a transceiver in simplex systems.
6.3.2 Receiver
The SC28L92 is conditioned to receive data when enabled through the command register.
The receiver looks for a HIGH-to-LOW (mark-to-space) transition of the start bit on the
RxD input pin. If a transition is detected, the state of the RxD pin is sampled each 16×
clock for 7 clocks to
1
⁄
2
clocks (16× clock mode) or at the next rising edge of the bit time
clock (1× clock mode). If RxD is sampled HIGH, the start bit is invalid and the search for a
valid start bit begins again. If RxD is still LOW, a valid start bit is assumed and the receiver
continues to sample the input at one bit time intervals at the theoretical center of the bit,
until the proper number of data bits and parity bit (if any) have been assembled, and one
stop bit has been detected. The least significant bit is received first. The data is then
transferred to the receive FIFO and the RxRDY bit in the SR is set to a 1. This condition
can be programmed to generate an interrupt at OP4 or OP5 and INTRN. If the character
length is less than 8 bits, the most significant unused bits in the Rx FIFO are set to zero.
After the stop bit is detected, the receiver will immediately look for the next start bit.
However, if a non-zero character was received without a stop bit (framing error) and RxD
remains LOW for one half of the bit period after the stop bit was sampled, then the
receiver operates as if a new start bit transition had been detected at that point (one-half
bit time after the stop bit was sampled).
The parity error, framing error and overrun error (if any) are strobed into the SR from the
next byte to be read from the Rx FIFO. If a break condition is detected (RxD is LOW for
the entire character including the stop bit), a character consisting of all zeros will be
loaded into the Rx FIFO and the received break bit in the SR is set to 1. The RxD input
must return to HIGH for two (2) clock edges of the X1 crystal clock for the receiver to
recognize the end of the break condition and begin the search for a start bit.
This will usually require a HIGH time of one X1 clock period or 3 X1 edges since the
clock of the controller is not synchronous to the X1 clock.
6.3.3 Transmitter reset and disable
Note the difference between transmitter disable and reset. A transmitter reset stops
transmitter action immediately, clears the transmitter FIFO and returns the idle state. A
transmitter disable withdraws the transmitter interrupts but allows the transmitter to
continue operation until all bytes in its FIFO and shift register have been transmitted
including the final stop bits. It then returns to its idle state.
SC28L92_7 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 07 — 19 December 2007 20 of 73
NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
6.3.4 Receiver FIFO
The Rx FIFO consists of a First-In-First-Out (FIFO) stack with a capacity of 8 or 16
characters. Data is loaded from the receive shift register into the topmost empty position
of the FIFO. The RxRDY bit in the status register is set whenever one or more characters
are available to be read, and a FFULL status bit is set if all 8 or 16 stack positions are filled
with data. Either of these bits can be selected to cause an interrupt. A read of the Rx FIFO
outputs the data at the top of the FIFO. After the read cycle, the data FIFO and its
associated status bits (see Section 6.3.5) are popped thus emptying a FIFO position for
new data.
A disabled receiver with data in its FIFO may generate an interrupt (see Section 6.3.5). Its
status bits remain active and its watchdog, if enabled, will continue to operate.
6.3.5 Receiver status bits
In addition to the data word, three status bits (parity error, framing error and received
break) are also appended to each data character in the FIFO. The overrun error, MR1[5],
is not FIFOed.
Status can be provided in two ways, as programmed by the error mode control bit in the
mode register. In the character mode, status is provided on a character-by-character
basis; the status applies only to the character at the top of the FIFO. In the block mode,
the status provided in the SR for these three bits is the logic OR of the status for all
characters coming to the top of the FIFO since the last reset error from the command
register was issued. In either mode reading the SR does not affect the FIFO. The FIFO is
popped only when the Rx FIFO is read. Therefore the status register should be read prior
to reading the FIFO.
If the FIFO is full when a new character is received, that character is held in the receive
shift register until a FIFO position is available. If an additional character is received while
this state exits, the contents of the FIFO are not affected; the character previously in the
shift register is lost and the overrun error status bit (SR[4]) will be set upon receipt of the
start bit of the new (overrunning) character.
The receiver can control the deactivation of RTS. If programmed to operate in this mode,
the RTSN output will be negated when a valid start bit was received and the FIFO is full.
When a FIFO position becomes available, the RTSN output will be reasserted (set LOW)
automatically. This feature can be used to prevent an overrun, in the receiver, by
connecting the RTSN output to the CTSN input of the transmitting device.
If the receiver is disabled, the FIFO characters can be read. However, no additional
characters can be received until the receiver is enabled again. If the receiver is reset, the
FIFO and all of the receiver status, and the corresponding output ports and interrupt are
reset. No additional characters can be received until the receiver is enabled again.
6.3.6 Receiver reset and disable
Receiver disable stops the receiver immediately. Data being assembled in the receiver
shift register is lost. Data and status in the FIFO is preserved and may be read. A
re-enable of the receiver after a disable will cause the receiver to begin assembling
characters at the next start bit detected.
SC28L92_7 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 07 — 19 December 2007 21 of 73
NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
A receiver reset will discard the present shift register date, reset the receiver ready bit
(RxRDY), clear the status of the byte at the top of the FIFO and realign the FIFO
read/write pointers.
6.3.7 Watchdog
A watchdog timer is associated with each receiver. Its interrupt is enabled by MR0[7]. The
purpose of this timer is to alert the control processor that characters are in the Rx FIFO
which have not been read. This situation may occur at the end of a transmission when the
last few characters received are not sufficient to cause an interrupt.
This counter times out after 64 bit times. It is reset each time a character is transferred
from the receiver shift register to the Rx FIFO or a read of the Rx FIFO is executed.
6.3.8 Receiver time-out mode
In addition to the watchdog timer described in Section 6.3.7, the counter/timer may be
used for a similar function. Its programmability, of course, allows much greater precision of
time-out intervals.
The time-out mode uses the received data stream to control the counter. Each time a
received character is transferred from the shift register to the Rx FIFO, the counter is
restarted. If a new character is not received before the counter reaches zero count, the
counter ready bit is set, and an interrupt can be generated. This mode can be used to
indicate when data has been left in the Rx FIFO for more than the programmed time limit.
Otherwise, if the receiver has been programmed to interrupt the CPU when the receive
FIFO is full, and the message ends before the FIFO is full, the CPU may not know there is
data left in the FIFO. The CTU and CTL value would be programmed for just over one
character time, so that the CPU would be interrupted as soon as it has stopped receiving
continuous data. This mode can also be used to indicate when the serial line has been
marking for longer than the programmed time limit. In this case, the CPU has read all of
the characters from the FIFO, but the last character received has started the count. If
there is no new data during the programmed time interval, the counter ready bit will get
set, and an interrupt can be generated.
The time-out mode is enabled by writing the appropriate command to the command
register. Writing 0xA to CRA or CRB will invoke the time-out mode for that channel.
Writing 0xC to CRA or CRB will disable the time-out mode. The time-out mode should
only be used by one channel at once, since it uses the C/T. If, however, the time-out mode
is enabled from both receivers, the time-out will occur only when both receivers have
stopped receiving data for the time-out period. CTU and CTL must be loaded with a value
greater than the normal receive character period. The time-out mode disables the regular
start counter or stop counter commands and puts the C/T into counter mode under the
control of the received data stream. Each time a received character is transferred from the
shift register to the Rx FIFO, the C/T is stopped after one C/T clock, reloaded with the
value in CTU and CTL and then restarted on the next C/T clock. If the C/T is allowed to
end the count before a new character has been received, the counter ready bit, ISR[3], will
be set. If IMR[3] is set, this will generate an interrupt. Receiving a character after the C/T
has timed out will clear the counter ready bit, ISR[3], and the interrupt. Invoking the set
time-out mode on command, CRx = 0xA, will also clear the counter ready bit and stop the
counter until the next character is received.
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SC28L92A1BS,551

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Buy SC28L92A1BS,551
Manufacturer:
NXP Semiconductors
Description:
IC UART DUAL W/FIFO 48HVQFN
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