SC28L92A1BS,551 Datasheet SC28L92A1B,551, SC28L92A1B,528, SC28L92A1BS,551 | P4-P6

Product data sheet Rev. 07 — 19 December 2007 4 of 73

NXP Semiconductors

SC28L92

3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter

4. Block diagram

The data pins TxD and RxD are considered idle at the logic 1 (HIGH) level when inactive, or active when at the logic 0

(LOW) level. Comments about these levels when RS232 is referenced often refer to Mark and Space levels. Mark usually

means inactive and Space means active. The voltage levels represented by the terms Mark and Space are often reversed

from those above: Mark is low voltage, and Space is high voltage.

Fig 1. Block diagram (80xxx mode)

SC28L92 (80xxx mode)

002aad459

BUS BUFFER

CHANNEL B

(AS ABOVE)

D0 to D7

OPERATION

CONTROL

ADDRESS

DECODE

R/W CONTROL

RESET

I/M

open or connect

to V

for 80xxx

A0 to A3

CEN

WRN

RDN

INTERRUPT

CONTROL

IMR

ISR

TIMING

BAUD RATE

GENERATOR

CLOCK

SELECTORS

COUNTER/

TIMER

XTAL

OSCILLATOR

CSRA

CSRB

ACR

CTL

CTU

INTRN

X1/CLK

INTERNAL DATA BUS

CHANNEL A

16-BYTE

TRANSMIT FIFO

TRANSMIT

SHIFT REGISTER

16-BYTE

RECEIVE FIFO

WATCHDOG

TIMER

TxDA

RxDA

RxDB

RECEIVE

SHIFT REGISTER

MRA0, 1, 2, 3

CRA

SRA

INPUT PORT

CHANGE-OF-

STATE

DETECTORS (4)

ACR

IPCR

IP0 to IP6

TxDB

OUTPUT PORT

FUNCTION

SELECT LOGIC

OPR

OPCR

OP0 to OP7

timing

control

Product data sheet Rev. 07 — 19 December 2007 5 of 73

NXP Semiconductors

SC28L92

3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter

The data pins TxD and RxD are considered idle at the logic 1 (HIGH) level when inactive, or active when at the logic 0

(LOW) level. Comments about these levels when RS232 is referenced often refer to Mark and Space levels. Mark usually

means inactive and Space means active. The voltage levels represented by the terms Mark and Space are often reversed

from those above: Mark is low voltage, and Space is high voltage.

Fig 2. Block diagram (68xxx mode)

SC28L92 (68xxx mode)

002aad460

BUS BUFFER

CHANNEL B

(AS ABOVE)

D0 to D7

OPERATION

CONTROL

ADDRESS

DECODE

R/W CONTROL

RESETN

I/M

ground for

68xxx mode

A0 to A3

CEN

IACKN

R/WN

INTERRUPT

CONTROL

IMR

ISR

TIMING

BAUD RATE

GENERATOR

CLOCK

SELECTORS

COUNTER/

TIMER

XTAL

OSCILLATOR

CSRA

CSRB

ACR

CTL

CTU

INTRN

X1/CLK

INTERNAL DATA BUS

CHANNEL A

16-BYTE

TRANSMIT FIFO

TRANSMIT

SHIFT REGISTER

16-BYTE

RECEIVE FIFO

WATCHDOG

TIMER

TxDA

RxDA

RxDB

RECEIVE

SHIFT REGISTER

MRA0, 1, 2, 3

CRA

SRA

INPUT PORT

CHANGE-OF-

STATE

DETECTORS (4)

ACR

IPCR

IP0 to IP5

TxDB

OUTPUT PORT

FUNCTION

SELECT LOGIC

OPR

OPCR

OP0 to OP7

timing

control

DACKN

Product data sheet Rev. 07 — 19 December 2007 6 of 73

NXP Semiconductors

SC28L92

3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter

5. Pinning information

5.1 Pinning

Fig 3. Pin conﬁguration for PLCC44; 80xxx mode

Fig 4. Pin conﬁguration for PLCC44; 68xxx mode

SC28L92A1A

(80xxx mode)

A3 CEN

IP0 RESET

WRN X2

RDN X1/CLK

RxDB RxDA

I/M n.c.

TxDB TxDA

OP1 OP0

OP3 OP2

OP5 OP4

OP7 OP6

D1 A2

D3 IP1

D5 A1

D7 IP3

GND A0

n.c. n.c.

INTRN V

D6 IP4

D4 IP5

D2 IP6

D0 IP2

002aad412

SC28L92A1A

(68xxx mode)

A3 CEN

IP0 RESETN

R/WN X2

DACKN X1/CLK

RxDB RxDA

I/M n.c.

TxDB TxDA

OP1 OP0

OP3 OP2

OP5 OP4

OP7 OP6

D1 A2

D3 IP1

D5 A1

D7 IP3

GND A0

n.c. n.c.

INTRN V

D6 IP4

D4 IP5

D2 IACKN

D0 IP2

002aad413

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P51 P52-P54 P55-P57 P58-P60 P61-P63 P64-P66 P67-P69 P70-P72 P73-P73

SC28L92A1BS,551

Mfr. #:

Buy SC28L92A1BS,551

Manufacturer:

NXP Semiconductors

Description:

IC UART DUAL W/FIFO 48HVQFN

Lifecycle:

New from this manufacturer.

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SC28L92A1BS,551

SC28L92A1BS,551

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