SC28L92_7 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 07 — 19 December 2007 57 of 73
NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
[1] The following conditions apply:
a) Parameters are valid over specified temperature and voltage range.
b) All voltage measurements are referenced to ground. For testing, all inputs swing between 0.4 V and 3.0 V with a transition time of
5 ns maximum. For X1/CLK this swing is between 0.4 V and 0.8V
CC
. All time measurements are referenced at input voltages of 0.8 V
and 2.0 V, and output voltages of 0.8 V and 2.0 V, as appropriate.
c) Test conditions for outputs: C
L
= 125 pF, except open-drain outputs. Test conditions for open-drain outputs: C
L
= 125 pF,
constant current source = 2.6 mA.
d) Typical values are the average values at +25 °C and 3.3 V.
[2] Timing is illustrated and referenced to the WRN and RDN Inputs. Also, CEN may be the strobing input. CEN and RDN (also CEN and
WRN) are ORed internally. The signal asserted last initiates the cycle and the signal negated first terminates the cycle.
[3] Guaranteed by characterization of sample units.
[4] If CEN is used as the strobing input, the parameter defines the minimum HIGH times between one CEN and the next. The RDN signal
must be negated for t
RWD
to guarantee that any status register changes are valid.
[5] Minimum frequencies are not tested but are guaranteed by design.
[6] Clocks for 1× mode should maintain a 60/40 duty cycle or better.
Clock timing (see Figure 17)
t
CLK
X1/CLK HIGH or LOW time 35 25 - ns
f
CLK
X1/CLK frequency
[5]
0.1 3.686 8 MHz
t
CTC
C/T clock (IP2) HIGH or LOW time (C/T
external clock input)
30 15 - ns
f
CTC
C/T clock (IP2) frequency
[5]
0- 8MHz
t
RX
RxC HIGH or LOW time 16× 30 10 - ns
f
RX
RxC frequency 16× 0 - 16 MHz
1×
[5][6]
0- 1MHz
t
TX
TxC HIGH or LOW time 16× 30 15 - ns
f
TX
TxC frequency 16× --16MHz
1×
[5][6]
0- 1MHz
Transmitter timing, external clock (see
Figure 18)
t
TXD
TxD output delay from TxC LOW (TxC
input pin)
- 4078ns
t
TCS
output delay from TxC output pin LOW to
TxD data output
- 8 30 ns
Receiver timing, external clock (see
Figure 19)
t
RXS
RxD data set-up time to RxC HIGH 50 10 - ns
t
RXH
RxD data hold time from RxC HIGH 50 10 - ns
68xxx or Motorola bus timing (see
Figure 12, 13 and 14)
[7]
t
DCR
DACKN LOW (read cycle) from X1 HIGH
[7]
- 1857ns
t
DCW
DACKN LOW (write cycle) from X1 HIGH - 18 57 ns
t
DAT
DACKN high-impedance from CEN or
IACKN HIGH
- 1015ns
t
CSC
CEN or IACKN set-up time to X1 HIGH for
minimum DACKN cycle
30 10 - ns
Table 68. Dynamic characteristics, 3.3 V operation
[1]
…continued
V
CC
= 3.3 V
±
10 %, T
amb
=
−
40
°
C to +85
°
C, unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
