SC28L92_7 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 07 — 19 December 2007 58 of 73
NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
[7] Minimum DACKN time is ((t
DCR
or t
DCW
)t
CSC
+ 2 X1 edges + rise time over 5 ns). Two X1 edges is 273 ns at 3.6864 MHz. For faster bus
cycles, the 80xxx bus timing may be used while in the 68xxx mode. It is not necessary to wait for DACKN to insure the proper operation
of the SC26C92. In all cases the data will be written to the SC28L92 on the falling edge of DACKN or the rise of CEN. The fall of CEN
initializes the bus cycle. The rise of CEN ends the bus cycle. DACKN LOW or CEN HIGH completes the write cycle.
11. Timing diagrams
a. 80xxx mode b. 68xxx mode
Fig 10. Reset timing
Fig 11. Bus timing (80xxx mode)
001aae303
RESET
t
RES
001aae304
RESETN
t
RES
A0 to A3
CEN
RDN
D0 to D7
(read)
WDN
D0 to D7
(write)
valid
validnot valid floatfloat
001aae305
t
AS
t
CS
t
CS
t
AH
t
RW
t
DD
t
DF
t
RWD
t
RWD
t
DH
t
DS
