SC28L92A1BS,551

SC28L92_7 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 07 — 19 December 2007 16 of 73

NXP Semiconductors

Often this division will result in a non-integer number; 26.3 for example. One may only

In the counter mode the counter/timer counts the value of the CTLR CTUR down to zero

and then sets the ISR[3] bit and sets the counter/timer output from 1 to 0. It then rolls over

to 65,365 and continues counting with no further observable effect. Reading the C/T in the

counter mode outputs the present state of the C/T. If the C/T is not stopped, a read of the

C/T may result in changing data on the data bus.

The time-out mode uses the received data stream to control the counter. The time-out

mode forces the C/T into the timer mode. Each time a received character is transferred

from the shift register to the Rx FIFO, the counter is restarted. If a new character is not

received before the counter reaches zero count, the counter ready bit is set, and an

above situation could be avoided. The processor would be interrupted any time the data

stream had stopped for more than one character time. Note: This is very similar to the

watchdog time of MR0. The difference is in the programmability of the delay time and that

the watchdog timer is restarted by either a receiver load to the Rx FIFO or a system read

from it.

This mode is enabled by writing the appropriate command to the command register.

Writing 0xA to CRA or CRB will invoke the time-out mode for that channel. Writing 0xC to

CRA or CRB will disable the time-out mode. Only one receiver should use this mode at a

time. However, if both are on, the time-out occurs after both receivers have been inactive

for the time-out period. The start of the C/T will be on the logic OR of the two receivers.

interrupt. Since receiving a character restarts the C/T, the receipt of a character after the

C/T has timed out will clear the counter ready bit, ISR[3], and the interrupt. Invoking the

Set Time-out Mode On command, CRx = 0xA, will also clear the counter ready bit and

stop the counter until the next character is received. The counter/timer is controlled with

six commands: Start/Stop C/T, Read/Write Counter/Timer lower register and Read/Write

SC28L92_7 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 07 — 19 December 2007 17 of 73

NXP Semiconductors

Counter/Timer upper register. These commands have slight differences depending on the

interrupt service begins for the previously seen interrupt, a read of the ISR will show the

Counter Ready bit not set. If nothing else is interrupting, this read of the ISR will return a

the RxD pin, converts this serial input to parallel format, checks for start bit, stop bit, parity

FIFOed with each data character.

The inputs to this unlatched 7-bit (6-bit for 68xxx mode) port can be read by the CPU by

performing a read operation at address 0xD. A HIGH input results in a logic 1 while a LOW

input results in a logic 0. D7 will always read as a logic 1. The pins of this port can also

serve as auxiliary inputs to certain portions of the DUART logic, modem and DMA.

Four change-of-state detectors are provided which are associated with inputs IP3, IP2,

IP1 and IP0. A HIGH-to-LOW or LOW-to-HIGH transition of these inputs, lasting longer

than 25 µs to 50 µs, will set the corresponding bit in the input port change register. The

bits are cleared when the register is read by the CPU. Any change of state can also be

The 50 µs time refers to the situation in which the change of state is just missed and the

first change of state is not detected until 25 µs later.

SC28L92_7 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 07 — 19 December 2007 18 of 73

NXP Semiconductors

the MR and CR registers. When the OPR is the source of the data for the output ports, the

data at the ports is inverted from that in the OPR register. The content of the OPR register

is controlled by the set output port bits command and the reset output bits command.

These commands are at 0xE and 0xF, respectively. When these commands are used,

action takes place only at the bit locations where ones exist. For example, a one in bit

location 5 of the data word used with the set output port bits command will result in OPR5

being set to one. The OP5 would then be set to zero (V

of the data word associated with the reset output ports bits command would set OPR5 to

zero and, hence, the pin OP5 to a one (V

These pins along with the IP pins and their change-of-state detectors are often used for

programmed to generate an interrupt request at OP6 or OP7 and INTRN. When the

transmitter is initially enabled the TxRDY and TxEMPT bits will be set in the status

register. When a character is loaded to the transmit FIFO the TxEMPT bit will be reset.

The TxEMPT will not set until: 1) the transmit FIFO is empty and the transmit shift register

has finished transmitting the stop bit of the last character written to the transmit FIFO, or

2) the transmitter is disabled and then re-enabled. The TxRDY bit is set whenever the

transmitter is enabled and the Tx FIFO is not full. Data is transferred from the holding

register to transmit shift register when it is idle or has completed transmission of the

previous character. Characters cannot be loaded into the Tx FIFO while the transmitter is

disabled.

If the transmitter is disabled it continues operating until the character currently being

transmitted and any characters in the Tx FIFO, including parity and stop bits, have been

transmitted. New data cannot be loaded to the Tx FIFO when the transmitter is disabled.

When the transmitter is reset it stops sending data immediately.