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SC28L92A1BS,551

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P73
SC28L92_7 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 07 — 19 December 2007 43 of 73
NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
7.3.8 Output Port Register (OPR)
Table 50. OPR - Output port register (no address) bit allocation
The output pins (OP pins) drive the complement of the data in this register as controlled by SOPR
and ROPR.
7 6 5 4 3 2 1 0
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
Table 51. OPR - Output port register (no address) bit description
Bit Symbol Description
7 - pin OP7
0 = pin HIGH
1 = pin LOW
6 - pin OP6
0 = pin HIGH
1 = pin LOW
5 - pin OP5
0 = pin HIGH
1 = pin LOW
4 - pin OP4
0 = pin HIGH
1 = pin LOW
3 - pin OP3
0 = pin HIGH
1 = pin LOW
2 - pin OP2
0 = pin HIGH
1 = pin LOW
1 - pin OP1
0 = pin HIGH
1 = pin LOW
0 - pin OP0
0 = pin HIGH
1 = pin LOW
SC28L92_7 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 07 — 19 December 2007 44 of 73
NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
7.3.9 Auxiliary Control Register (ACR)
[1] The timer mode generates a square wave.
Table 52. ACR - Auxiliary control register (address 0x4) bit allocation
7 6 5 4 3 2 1 0
BRG set
select
counter/timer mode and clock source select enable IP3
COS interrupt
enable IP2
COS interrupt
enable IP1
COS interrupt
enable IP0
COS interrupt
Table 53. ACR - Auxiliary control register (address 0x4) bit description
Bit Symbol Description
7 - Baud rate generator set select.
This bit selects one of two sets of baud rates to be generated by the BRG (see
Table 35).
The selected set of rates is available for use by the channel A and B receivers
and transmitters as described for CSRA in
Table 34 and for CSRB in Table 37.
Baud rate generator characteristics are given in
Table 36.
6 to 4 - Counter/timer mode and clock source select.
This field selects the operating mode of the counter/timer and its clock source
as shown in
Table 54.
3 to 0 - IP3, IP2, IP1 and IP0 change-of-state interrupt enable.
0 = off
1 = enabled
This field selects which bits of the input port change register (IPCR) cause the
input change bit in the interrupt status register (ISR [7]) to be set. If a bit is in
the enabled state the setting of the corresponding bit in the IPCR will also
result in the setting of ISR [7], which results in the generation of an interrupt
output if IMR [7] = 1. If a bit is in the off state, the setting of that bit in the IPCR
has no effect on ISR [7].
Table 54. ACR[6:4] field definition
[1]
ACR[6:4] Mode Clock source
000 counter external (IP2)
001 counter TxCA - 1× clock of channel A transmitter
010 counter TxCB - 1× clock of channel B transmitter
011 counter crystal or external clock (X1/CLK) divided by 16
100 timer external (IP2)
101 timer external (IP2) divided by 16
110 timer crystal or external clock (X1/CLK)
111 timer crystal or external clock (X1/CLK) divided by 16
SC28L92_7 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 07 — 19 December 2007 45 of 73
NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
7.3.10 Input Port Change Register (IPCR)
7.3.11 Interrupt Status Register (ISR)
This register provides the status of all potential interrupt sources. The contents of this
register are masked by the Interrupt Mask Register (IMR). If a bit in the ISR is a logic 1
and the corresponding bit in the IMR is also a logic 1, the INTRN output will be asserted
(LOW). If the corresponding bit in the IMR is a zero, the state of the bit in the ISR has no
effect on the INTRN output. Note that the IMR does not mask the reading of the ISR. The
true status will be provided regardless of the contents of the IMR. The contents of this
register are initialized to 0x0 when the DUART is reset.
Table 55. IPCR - Input port change register (address 0x4) bit allocation
7 6 5 4 3 2 1 0
delta IP3 delta IP2 delta IP1 delta IP0 state of
IP3
state of
IP2
state of
IP1
state of
IP0
Table 56. IPCR - Input port change register (address 0x4) bit description
Bit Symbol Description
7 to 4 - IP3, IP2, IP1 and IP0 change of state.
0 = no change
1 = change
These bits are set when a change of state, as defined in
Section 6.2.9 “Input
port”, occurs at the respective input pins. They are cleared when the IPCR is
read by the CPU. A read of the IPCR also clears ISR[7], the input change bit in
the interrupt status register. The setting of these bits can be programmed to
generate an interrupt to the CPU.
3 to 0 - IP3, IP2, IP1 and IP0 state.
0 = LOW
1 = HIGH
These bits provide the current state of the respective inputs. The information is
unlatched and reflects the state of the input pins at the time the IPCR is read.
Table 57. ISR - Interrupt status register (address 0x5) bit allocation
7 6 5 4 3 2 1 0
change
input port
change
break B
RxRDYB TxRDYB counter
ready
change
break A
RxRDYA TxRDYA
Table 58. ISR - Interrupt status register (address 0x5) bit description
Bit Symbol Description
7 - Input port change status.
0 = not active
1 = active
This bit is a logic 1 when a change of state has occurred at the IP0, IP1, IP2, or
IP3 inputs and that event has been selected to cause an interrupt by the
programming of ACR[3:0]. The bit is cleared when the CPU reads the IPCR.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P73

SC28L92A1BS,551

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Manufacturer:
NXP Semiconductors
Description:
IC UART DUAL W/FIFO 48HVQFN
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